JPS59113841U - Main memory configuration controller - Google Patents
Main memory configuration controllerInfo
- Publication number
- JPS59113841U JPS59113841U JP18976883U JP18976883U JPS59113841U JP S59113841 U JPS59113841 U JP S59113841U JP 18976883 U JP18976883 U JP 18976883U JP 18976883 U JP18976883 U JP 18976883U JP S59113841 U JPS59113841 U JP S59113841U
- Authority
- JP
- Japan
- Prior art keywords
- main memory
- selection information
- unit selection
- configuration unit
- storage means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による実施例の主記憶制御装置を示す図
、第２図および第３図は構成選択ＲＡＭの記憶内容の例
を示す図である。図中、１は主記憶装置、２は中央処理
装置、３は構成単位選択情報作成装置、４は主記憶部、
・５は主記憶制御部、６〜１３は第１構成単位〜第８構
成単位、１４はアクセス制御およびタイミング発生回路
、１５はアドレス制御回路、１６は読み出しデータ回路
、１７は書き込みデータ回路、１８は構成選択ＲＡＭア
ドレス制御回路、１９は構成選択ＲＡＭ。
２０は構成選択ＲＡＭアクセス制御回路、２１はアクセ
ス制御および分配回路である。FIG. 1 is a diagram showing a main memory control device according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing examples of storage contents of a configuration selection RAM. In the figure, 1 is a main memory, 2 is a central processing unit, 3 is a constituent unit selection information creation device, 4 is a main memory,
・5 is a main memory control unit, 6 to 13 are first to eighth structural units, 14 is an access control and timing generation circuit, 15 is an address control circuit, 16 is a read data circuit, 17 is a write data circuit, 18 19 is a configuration selection RAM address control circuit; and 19 is a configuration selection RAM. 20 is a configuration selection RAM access control circuit, and 21 is an access control and distribution circuit.
Claims (1)
が主記憶制御部と主記憶部から構成されかつ該主記憶部
は同時に記憶情報の読み出し、書込みをする複数の構成
単位により構成されているデータ処理システムにおいて
、中央処理装置からのアドレスに基いて構成単位選択情
報を発生する書き換え可能な構成単位選択情報記憶手段
と、主記憶装置外にもうけられた構成単位選択情報作成
装置から送出される構成単位選択情報の上記記憶手段は
の書き込みおよび中央処理装置からのアドレスにもとす
く上記記憶手段からの読み出しを制御する構成単位選択
制御回路をそなえ、該構成単位選択制御回路の制御によ
り、構成単位選択情報を上記記憶手段へ書込むとともに
、上記記憶手段から構成単位選択情報を読み出し、主記
憶部へのアクセスを行なうように構成したことを特徴と
する主記憶構成制御装置。In the connection between the central processing unit and the main memory device, the main memory device is composed of a main memory control section and a main memory section, and the main memory section is composed of a plurality of structural units that read and write stored information at the same time. In a data processing system, the configuration unit selection information is sent from a rewritable configuration unit selection information storage means that generates configuration unit selection information based on an address from the central processing unit, and a configuration unit selection information creation device provided outside the main memory. The storage means for the configuration unit selection information is provided with a configuration unit selection control circuit for controlling the writing of the configuration unit selection information and the reading from the storage unit at the address from the central processing unit. A main memory configuration control device, characterized in that it is configured to write unit selection information into the storage means, read out the constituent unit selection information from the storage means, and access the main storage section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18976883U JPS59113841U (en) | 1983-12-08 | 1983-12-08 | Main memory configuration controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18976883U JPS59113841U (en) | 1983-12-08 | 1983-12-08 | Main memory configuration controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59113841U true JPS59113841U (en) | 1984-08-01 |
Family
ID=30409061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18976883U Pending JPS59113841U (en) | 1983-12-08 | 1983-12-08 | Main memory configuration controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59113841U (en) |
-
1983
- 1983-12-08 JP JP18976883U patent/JPS59113841U/en active Pending
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