JPS58166070A - Thermal head - Google Patents
Thermal headInfo
- Publication number
- JPS58166070A JPS58166070A JP57048866A JP4886682A JPS58166070A JP S58166070 A JPS58166070 A JP S58166070A JP 57048866 A JP57048866 A JP 57048866A JP 4886682 A JP4886682 A JP 4886682A JP S58166070 A JPS58166070 A JP S58166070A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor
- substrate
- heating resistor
- thermal head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/335—Structure of thermal heads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
Landscapes
- Combinations Of Printed Boards (AREA)
- Electronic Switches (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分舒）
本発明は、ファクシ建すやプリンタ等Ｏ感熱紀鍮装置に
用＾られるサーマルヘッドに関す石。DETAILED DESCRIPTION OF THE INVENTION (Technical division of the invention) The present invention relates to a thermal head used in O-thermal brass devices such as facsimile machines and printers.
（発明の技術的背景とその問題点）
従来、高速記倦用ず−マルヘッド紘嬉１１１に示すｊ’
に、絶縁ｓ板１ｔ）上Ｋｌｖ−ズー２、発熱抵抗体３、
第１層導体４、儂−膜Ｓ、耐摩耗膜６、絶縁１１１７、
第２層導体８．ドライバとジット・レジスタを集積し九
半導体嵩子９で構成されている。(Technical Background of the Invention and Problems Thereof) Conventionally, high-speed memory devices - j' shown in Marhead Hiroki 111
On the insulating s plate 1t) Klv-zoo 2, heating resistor 3,
First layer conductor 4, my film S, wear-resistant film 6, insulation 1117,
Second layer conductor 8. It is composed of nine semiconductor bulkheads 9 that integrate drivers and registers.
サーマルヘッドを実現する万機としては、第１図に示す
ように同一基板上に集積し丸集積方式と、発熱抵抗体基
板と多噛配線基板とを各々個別の基板に形成し、これら
の基板を支持板上に固定して基板間を接続するいわゆる
分割基板方式とがある。As shown in Figure 1, there are two ways to realize a thermal head: a round integration method in which the heating resistor board and a multi-layer wiring board are each formed on separate boards, and these boards are integrated on the same board. There is a so-called split board method in which the boards are fixed on a support plate and the boards are connected.
従来、この分割基板方式サーマルヘッドにおいて、発熱
抵抗体基板と多１−配置＠板との接続方法としては、ワ
イヤーボンディング法、ビームリード法、テープキャリ
ア法、レリップ法□などが用いられている。この４合、
高を解能を、しかも大型において要求されることが多い
ので、接続方法および接続技術が信頼性を確保する上で
極めて重要となっている。１！には、価格の面からも接
続方法の遺択が重要である。このような意味からワイヤ
ボｙディ／グ法は広＜ ５ＩｊＲｔ、 ’ｈして用い゛
られている。しかし、接続箇所が、例えば８ドツト／鴎
のＡ４版ヘッドの場合％ １７２８個の発熱抵抗体が存
在し、 ３４５６箇所の接続点とな秒、工数的に４、信
頼性的にも歇産的には非常に困−が多−０まえ、ビ−ム
リード法は信頼性的には優れているが、ａｍ面で問題が
ある□、壕九、テープキャリア法は多数のリードを一括
にダンディングする九め、工数的に有利で、信頼性爾お
よび領格面からもすぐれているが、特別のテープキャリ
アを必要とする欠点がある。Conventionally, in this split-substrate type thermal head, the wire bonding method, beam lead method, tape carrier method, relip method, etc. have been used as a method for connecting the heating resistor substrate and the multi-layer board. These 4 go,
Since high resolution and large size are often required, connection methods and technology are extremely important to ensure reliability. 1! The choice of connection method is also important from the standpoint of price. In this sense, the wire body digging method is widely used. However, if the connection points are, for example, an A4 size head with 8 dots/hook, there are 1,728 heating resistors and 3,456 connection points, which takes 4 seconds, takes 4 hours, and is not reliable. The beam lead method has excellent reliability but has problems in terms of AM. Although this method is advantageous in terms of man-hours, reliability, and performance, it has the disadvantage of requiring a special tape carrier.
この点では、７リツプチツプ法は工数的にも、材料的に
４非常に有利であるが、高密ＩＦＯＩｌｌ統電極杉成が
困−で、＾′ｑ！！暖の接続ができない欠点を有する。In this respect, the 7-lip chip method is very advantageous in terms of man-hours and materials, but it is difficult to build a high-density IFO Ill-type electrode. ! It has the disadvantage that it cannot be connected to a heating source.
（発明の目的）
本発明は、これらの従来の偏置の欠点Ｋｌｌみなされ丸
もので、量産、性にすぐ九九高置１の基板間接続を可能
くし九サーマルヘッドを提供すゐことを目的とする。(Object of the Invention) The present invention aims to overcome these drawbacks of the conventional eccentric positioning, and to provide a thermal head that can be mass-produced and easily connected between high-mounted substrates. purpose.
（発明の概要）
本発明の特徴は、発熱抵抗体着板と多層配線基板との関
に有機樹脂によるＩｌ！続補助−を拳成し、分割され先
発熱抵抗体基板と多層配線ａ１［とを薄膜技術によシ接
続するところｋｓする。(Summary of the Invention) A feature of the present invention is that an organic resin is used to connect the heating resistor to the multilayer wiring board! The first step is to connect the divided first heating resistor substrate and the multilayer wiring a1 by thin film technology.
（発明の実施例）
次Ｆｃ装置ｔ１４０実１１１例？ｃツｒテ、１１１２ｍ
−１１１４１Ｅｌの図面とともに詳細に説明する。(Embodiment of the invention) Next 111 actual examples of Fc device t140? C Tsurte, 1112m
-11141El will be explained in detail along with the drawings.
＠２図は発熱抵抗体基板を示す図である。１は絶縁基板
、２Ｆｉグレ一ズ層、３Ｆｉ発熱抵抗体であゆ１、スパ
ッタなどの方法でＴａ−８ｉ０２サーメツト薄膜が形成
され、ホトエツチング技術で１列に並んで個々の発熱抵
抗体に分割される。この発熱抵抗体に電流を供給する丸
めの第１−導体４け、Ｃｒ−Ａｕの２導凛着膜をエツチ
ングして得られる。Figure @2 is a diagram showing a heating resistor substrate. 1 is an insulating substrate, a 2Fi grating layer, a 3Fi heating resistor, and a Ta-8i02 cermet thin film is formed using a method such as sputtering, which is then lined up in a row and divided into individual heating resistors using a photo-etching technique. . Four rounded first conductors for supplying current to the heating resistor are obtained by etching a two-conductor deposited film of Cr--Au.
次に発熱抵抗体３を化学的に安定に保っ意味で保穫膜５
が形成される。Ｖ＜感熱紙との接触による摩耗を防ぐ九
めに耐摩耗１１６が形成される。保＃Ｉ＠５および耐摩
耗ｆｉｉ１６は部分的なマスクスパッタの方法で発熱抵
抗体３上に投ける。＠３図はマトリックス基板を示す図
である。１はセラミック基板、４は第１４導体、７は絶
縁−１８は嬉２−導体である。Next, a protective film 5 is used to keep the heating resistor 3 chemically stable.
is formed. A wear resistant layer 116 is formed at the ninth position to prevent wear due to contact with V<thermal paper. The protection #I@5 and the wear resistance fii16 are applied onto the heating resistor 3 by a partial mask sputtering method. @3 Figure is a diagram showing a matrix substrate. 1 is a ceramic substrate, 4 is a 14th conductor, 7 is an insulation board, and 18 is a 2nd conductor.
第４図は本発明のサーマルヘッドの一実施例を示す図で
ある。別個に作られ先発熱抵抗体基板とマ） ＋７ツク
ス基板とが支持板１０に各々基板の嬉１１４体４が突き
合せるように接着固定されて−る。FIG. 4 is a diagram showing an embodiment of the thermal head of the present invention. A separately manufactured first heating resistor substrate and a +7x substrate are adhesively fixed to a support plate 10 so that the respective substrates 114 are butted against each other.
接続補助ｌｉｔは、ポ、リイＺド樹脂のプレポリマーｆ
ＩＩＩＩＩｌを第１ｌ４体４に掛からないように発熱抵
抗基板と多層配線基板との間を填め込むようにコー、ト
、後３５０℃、窒素中でキ為アして形成する。＊続導体
１２は部分的なマスク蒸着法によるＣｒ−Ａｕの２１導
蒸着膜を発熱抵抗体基とマトリックス基板との第１１４
体に接続するようにホットエツチング技術で形成する。The connection auxiliary lit is made of prepolymer f of polymeric resin.
IIIIIIl is coated so as to fit between the heating resistor board and the multilayer wiring board so as not to cover the first l4 body 4, and then heated at 350° C. in nitrogen to form. *The connecting conductor 12 is a 21-conductor evaporated film of Cr-Au by a partial mask evaporation method, and the 114th conductor 12 is a 21-conductor evaporated film of Cr-Au, which is formed by a heating resistor base and a matrix substrate.
Formed using hot etching technology to connect to the body.
最後に１半導体素子９を＊＊してｆ４２層導層導とワイ
ヤポンディてグによる接続を行い、サーマルヘッドを構
成する。Finally, one semiconductor element 9 is connected to the F42 layer conductor by wire bonding to form a thermal head.
上記実施例においてはドフイパとシフト・レジスタを集
積し先手導体素子を実装したサーマルヘッドによ＃）説
明し九が、上記以外の半導体素子を実績したサーマルヘ
ッドに対しても適用可能である。In the above embodiment, a thermal head in which a driver and a shift register are integrated and a lead conductor element is mounted is described, but it is also applicable to a thermal head in which semiconductor elements other than those described above have been used.
（発明の効果）
本発明は上述のように発熱抵抗体ｔｉ＋Ｉ［と多層配線
基板との接続を薄膜技術で接続しているので量ｆｉｉｉ
Ｋすぐれた微細パターンの高密変の接続が容易になりサ
ーマルヘッドの生ａＳを高め、低価格のサーマルヘッド
が得られる。(Effects of the Invention) As described above, the present invention connects the heating resistor ti+I and the multilayer wiring board using thin film technology, so that
This makes it easy to connect high-density connections with excellent fine patterns, increases the raw aS of the thermal head, and provides a low-cost thermal head.
第１図は従来のサーマルヘッドの構造を示す斜視図、’
＠２＠は本発明の一実施例の発熱抵抗体基板の斜視図、
第３図はこの実施例の多−配線基板の斜゛視図、第４＠
はとの実施例のサーマルヘッドの斜視図である。
１・・・絶縁基板、３・・・発熱抵抗体、５・・・第１
ｌ４体、８・・・第２１１導体、９・・・半導体素子、
□１０・・・支持板、１１・・・接続補助−０代、雇
人 弁１士 則 近 憲 佑
（ほか１名）Figure 1 is a perspective view showing the structure of a conventional thermal head.
@2@ is a perspective view of a heating resistor substrate according to an embodiment of the present invention;
Figure 3 is a perspective view of the multi-wiring board of this embodiment, and Figure 4
FIG. 2 is a perspective view of a thermal head according to an embodiment of the present invention. 1... Insulating substrate, 3... Heat generating resistor, 5... First
l4 body, 8... 211th conductor, 9... semiconductor element,
□10...Support plate, 11...Connection assistance - 0s, employee, 1st lawyer, Kensuke Chika (and 1 other person)
Claims (1)
多層配線部を台々独立し九Ｓａ上に響成し、前記基板間
を有機系装置で欄め、且つ前５ｅｌｌ熱抵抗体部と前記
多層配線部とを薄膜配線で接続してなることを特徴とす
為サーマルヘッド。A plurality of nine O-cell body parts and multilayer wiring parts are arranged in a row on an insulating substrate, and each board is independently formed on a nine-sample board, and the space between the boards is lined with an organic device, and the front five-cell thermal resistance is arranged in a row. A thermal head characterized in that the body portion and the multilayer wiring portion are connected by thin film wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57048866A JPS58166070A (en) | 1982-03-29 | 1982-03-29 | Thermal head |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57048866A JPS58166070A (en) | 1982-03-29 | 1982-03-29 | Thermal head |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58166070A true JPS58166070A (en) | 1983-10-01 |
Family
ID=12815199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57048866A Pending JPS58166070A (en) | 1982-03-29 | 1982-03-29 | Thermal head |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58166070A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2652681A1 (en) * | 1989-10-03 | 1991-04-05 | Mitsubishi Electric Corp | METHOD FOR MAKING A COMBINED WIRING SUBSTRATE |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5749582A (en) * | 1980-09-11 | 1982-03-23 | Nec Corp | Thermal head |
-
1982
- 1982-03-29 JP JP57048866A patent/JPS58166070A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5749582A (en) * | 1980-09-11 | 1982-03-23 | Nec Corp | Thermal head |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2652681A1 (en) * | 1989-10-03 | 1991-04-05 | Mitsubishi Electric Corp | METHOD FOR MAKING A COMBINED WIRING SUBSTRATE |
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