JPS58156388U - Gate circuit of gate turn-off thyristor - Google Patents

Gate circuit of gate turn-off thyristor

Info

Publication number
JPS58156388U
JPS58156388U JP5329782U JP5329782U JPS58156388U JP S58156388 U JPS58156388 U JP S58156388U JP 5329782 U JP5329782 U JP 5329782U JP 5329782 U JP5329782 U JP 5329782U JP S58156388 U JPS58156388 U JP S58156388U
Authority
JP
Japan
Prior art keywords
gate
thyristor
circuit
turn
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5329782U
Other languages
Japanese (ja)
Inventor
渋谷 忠士
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP5329782U priority Critical patent/JPS58156388U/en
Publication of JPS58156388U publication Critical patent/JPS58156388U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のゲート回路を示す具体的な回路構成図、
第2図は本考案による一実施例を示すゲート回路の具体
的な回路構成図。 1はGTo、2はスナバ−回路、6は電圧検出回路、7
はANDゲート、Trl−Tr2ハトランジスタ、Rニ
ーR2は電流制限抵抗、El−E2は直流電源、pcは
フォトカプラ。
Figure 1 is a specific circuit configuration diagram showing a conventional gate circuit.
FIG. 2 is a specific circuit configuration diagram of a gate circuit showing one embodiment of the present invention. 1 is GTo, 2 is a snubber circuit, 6 is a voltage detection circuit, 7
is an AND gate, Trl-Tr2 is a transistor, R knee R2 is a current limiting resistor, El-E2 is a DC power supply, and pc is a photocoupler.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1のスイッチング素子を通してONゲート指令信号を
、第2のスイッチング素子を通してOFFゲート指令信
号をそれぞれ与えることによって、ゲートターンオフサ
イリスタを0N−OFF制御するようにしたものに於て
、ゲートターンオフサイリスタに並列接続されるスナバ
−回路のコンデンサ電圧を検出する検出回路と、コンデ
ンサ電圧が無電圧である旨の検出信号とOFFゲート指
令信号との論理積条件をとって、前記第2のスイッチン
グ素子にOFF指令を与える回路とて構成したことを特
徴とするゲートターンオフサイリスタのゲート回路。
Parallel to the gate turn-off thyristor in which the gate turn-off thyristor is controlled ON-OFF by applying an ON gate command signal through the first switching element and an OFF gate command signal through the second switching element. A detection circuit that detects the capacitor voltage of the connected snubber circuit takes an AND condition of a detection signal indicating that the capacitor voltage is no voltage and an OFF gate command signal, and issues an OFF command to the second switching element. A gate circuit for a gate turn-off thyristor, characterized in that it is configured as a circuit that provides the following.
JP5329782U 1982-04-13 1982-04-13 Gate circuit of gate turn-off thyristor Pending JPS58156388U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5329782U JPS58156388U (en) 1982-04-13 1982-04-13 Gate circuit of gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5329782U JPS58156388U (en) 1982-04-13 1982-04-13 Gate circuit of gate turn-off thyristor

Publications (1)

Publication Number Publication Date
JPS58156388U true JPS58156388U (en) 1983-10-19

Family

ID=30063971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5329782U Pending JPS58156388U (en) 1982-04-13 1982-04-13 Gate circuit of gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS58156388U (en)

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