JPS5754449A - Circuit device in slave station for time division multiplex signal transmission system - Google Patents
Circuit device in slave station for time division multiplex signal transmission systemInfo
- Publication number
- JPS5754449A JPS5754449A JP13042580A JP13042580A JPS5754449A JP S5754449 A JPS5754449 A JP S5754449A JP 13042580 A JP13042580 A JP 13042580A JP 13042580 A JP13042580 A JP 13042580A JP S5754449 A JPS5754449 A JP S5754449A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- noise
- slave station
- transmitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Noise Elimination (AREA)
Abstract
PURPOSE:To completely prevent malfunction due to noise mixed during transmission, by avoiding output to terminals until all of control signals are received to a selected slave station, discriminating if noise comes for the time, and outputting the control signal to the terminal depending on the presence. CONSTITUTION:A signal transmitted from a master station enters a wave shape circuit in a slave station and divided into CP1, CP2, and DATA signal. These signals are transmitted to a serial-parallel conversion circuit 1, and if the address detection circuit coincides at the 1st 8-th bit, a signal AD is outputted. This AD signal is led to a serial-parallel circuit 5 via FF2 to be set and an AND circuit 4, and the circuit 5 is controlled with a signal SRO. If noise is mixed, a signal NG is transmitted to an FF3 from a noise detection circuit, and an output NOL from the FF3 resets an FF8 via an OR circuit 10 to make zero the SPO output of an AND circuit 7. Thus, the gate of a tri-state buffer 9 remains closed and a stored control signal is not outputted to the terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13042580A JPS5754449A (en) | 1980-09-19 | 1980-09-19 | Circuit device in slave station for time division multiplex signal transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13042580A JPS5754449A (en) | 1980-09-19 | 1980-09-19 | Circuit device in slave station for time division multiplex signal transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5754449A true JPS5754449A (en) | 1982-03-31 |
Family
ID=15033932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13042580A Pending JPS5754449A (en) | 1980-09-19 | 1980-09-19 | Circuit device in slave station for time division multiplex signal transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5754449A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54159119A (en) * | 1978-06-07 | 1979-12-15 | Hitachi Ltd | Data transmission system |
-
1980
- 1980-09-19 JP JP13042580A patent/JPS5754449A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54159119A (en) * | 1978-06-07 | 1979-12-15 | Hitachi Ltd | Data transmission system |
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