JPS5729164A - Computer system - Google Patents
Computer systemInfo
- Publication number
- JPS5729164A JPS5729164A JP10384880A JP10384880A JPS5729164A JP S5729164 A JPS5729164 A JP S5729164A JP 10384880 A JP10384880 A JP 10384880A JP 10384880 A JP10384880 A JP 10384880A JP S5729164 A JPS5729164 A JP S5729164A
- Authority
- JP
- Japan
- Prior art keywords
- write
- signal
- bus
- writing
- indication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
PURPOSE:To set the number of protection blocks optionally by suppressing the writing of written data supplied from a data bus when a write inhibition signal is supplied via a write inhibition signal bus. CONSTITUTION:A CPU1 selects a storage device 5 on the basis of a write and read address supplied via an address bus 2, and indicates the reading and writing of data by a write and read signal supplied via a control signal bus 3. In this case, when write and read addresses from the CPU1 are included in protection addresses preset for memory protection, an address comparator 18 supplies a write inhibition signal to a write inhibition signal bus 19, and this signal is used to send the indication of the write inhibition of written data to the device 5. Consequently, the device 5 suppresses the writing of the written data by a write and indication signal supplied from the CPU1 via the bus 3 when the write and read indication signal shows the indication of writing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10384880A JPS5729164A (en) | 1980-07-29 | 1980-07-29 | Computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10384880A JPS5729164A (en) | 1980-07-29 | 1980-07-29 | Computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5729164A true JPS5729164A (en) | 1982-02-17 |
Family
ID=14364854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10384880A Pending JPS5729164A (en) | 1980-07-29 | 1980-07-29 | Computer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5729164A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6067224U (en) * | 1983-10-17 | 1985-05-13 | 高木 重時 | Movable body positioning device |
-
1980
- 1980-07-29 JP JP10384880A patent/JPS5729164A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6067224U (en) * | 1983-10-17 | 1985-05-13 | 高木 重時 | Movable body positioning device |
JPH0237283Y2 (en) * | 1983-10-17 | 1990-10-09 |
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