JPS57177551A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor

Info

Publication number
JPS57177551A
JPS57177551A JP56062431A JP6243181A JPS57177551A JP S57177551 A JPS57177551 A JP S57177551A JP 56062431 A JP56062431 A JP 56062431A JP 6243181 A JP6243181 A JP 6243181A JP S57177551 A JPS57177551 A JP S57177551A
Authority
JP
Japan
Prior art keywords
layer
solder
semiconductor device
emitter
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56062431A
Other languages
Japanese (ja)
Inventor
Mitsuo Ito
Nobukatsu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56062431A priority Critical patent/JPS57177551A/en
Publication of JPS57177551A publication Critical patent/JPS57177551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate wire bonding and insulating works between devices and a substrate by a method wherein a second semiconductor device is placed upon a first semiconductor device fixedly located on a supporting substrate and is directly bonded with the first electrically and mechanically. CONSTITUTION:The n collector layer 4 of a Darlington transistor chip 20 is fixed by solder 19 onto a metal supporting substrate 12. An n emitter layer 6 within a p base layer 5 is a driver emitter and is bonded by solder 21 to the base 5 of a power stage, and an n layer 7 is now a power stage emitter. Solder 22 and 23 are applied respectively onto the p layer 5 and then n layer 7. The p layer 25 of the diode chip 24 is bonded to the solder 21 and an n layer 26 to the solder 22. These bonding works are performed simultaneously with the solder reflow for the purpose of bonding the chip and the supporting substrate. With a large space created between the device 24 and the substrate 12, insulation is easily effected and addition of new wires can also be performed with ease.
JP56062431A 1981-04-27 1981-04-27 Semiconductor device and manufacturing method therefor Pending JPS57177551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56062431A JPS57177551A (en) 1981-04-27 1981-04-27 Semiconductor device and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56062431A JPS57177551A (en) 1981-04-27 1981-04-27 Semiconductor device and manufacturing method therefor

Publications (1)

Publication Number Publication Date
JPS57177551A true JPS57177551A (en) 1982-11-01

Family

ID=13199974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56062431A Pending JPS57177551A (en) 1981-04-27 1981-04-27 Semiconductor device and manufacturing method therefor

Country Status (1)

Country Link
JP (1) JPS57177551A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1914805A2 (en) 1998-11-30 2008-04-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor power module
CN109530957A (en) * 2017-09-21 2019-03-29 丰田自动车株式会社 Grafting material

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1914805A2 (en) 1998-11-30 2008-04-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor power module
EP1914805A3 (en) * 1998-11-30 2008-05-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor power module
CN109530957A (en) * 2017-09-21 2019-03-29 丰田自动车株式会社 Grafting material

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