JPS56145583A - Buffer memory device - Google Patents

Buffer memory device

Info

Publication number
JPS56145583A
JPS56145583A JP5016080A JP5016080A JPS56145583A JP S56145583 A JPS56145583 A JP S56145583A JP 5016080 A JP5016080 A JP 5016080A JP 5016080 A JP5016080 A JP 5016080A JP S56145583 A JPS56145583 A JP S56145583A
Authority
JP
Japan
Prior art keywords
buffer memory
address
indexing
page
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5016080A
Other languages
Japanese (ja)
Other versions
JPS6028016B2 (en
Inventor
Kiyoshi Morishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55050160A priority Critical patent/JPS6028016B2/en
Publication of JPS56145583A publication Critical patent/JPS56145583A/en
Publication of JPS6028016B2 publication Critical patent/JPS6028016B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To eliminate the time required for indexing of a translation look-aside buffer to improve the performance of an information processing device, by indexing the buffer memory by a virtual address. CONSTITUTION:When directories of translation look-aside buffers 2a and 2b corresponding to the access by the address of virtural page storing register 1b coincide with the page information of virtual page storing register 1a in comparators 4a and 4b, virtual addresses from registers 1a and 1b and register 1c, in which the address in the page is stored, are applied to buffer memory directories 15a... by control part 20, and write data is written to one of buffer memory data storages 9a... at the write request time in accordance with coincidence due to one of comparators 11a.... Data is read similarly at the read request time, and thus, the buffer memory is indexed without converting the virtual address to an actual address, and the time required for indexing of the translation look-aside buffer is eliminated to improve the information processing performance.
JP55050160A 1980-04-15 1980-04-15 buffer storage device Expired JPS6028016B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55050160A JPS6028016B2 (en) 1980-04-15 1980-04-15 buffer storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55050160A JPS6028016B2 (en) 1980-04-15 1980-04-15 buffer storage device

Publications (2)

Publication Number Publication Date
JPS56145583A true JPS56145583A (en) 1981-11-12
JPS6028016B2 JPS6028016B2 (en) 1985-07-02

Family

ID=12851436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55050160A Expired JPS6028016B2 (en) 1980-04-15 1980-04-15 buffer storage device

Country Status (1)

Country Link
JP (1) JPS6028016B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150186A (en) * 1982-03-03 1983-09-06 Nec Corp System for controlling buffer memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150186A (en) * 1982-03-03 1983-09-06 Nec Corp System for controlling buffer memory
JPS6213699B2 (en) * 1982-03-03 1987-03-28 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6028016B2 (en) 1985-07-02

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