JPS554726A - Pcm signal recording method - Google Patents

Pcm signal recording method

Info

Publication number
JPS554726A
JPS554726A JP7617378A JP7617378A JPS554726A JP S554726 A JPS554726 A JP S554726A JP 7617378 A JP7617378 A JP 7617378A JP 7617378 A JP7617378 A JP 7617378A JP S554726 A JPS554726 A JP S554726A
Authority
JP
Japan
Prior art keywords
block
divided
pcm
parity
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7617378A
Other languages
Japanese (ja)
Other versions
JPH0239036B2 (en
Inventor
Toshitada Doi
Keiichi Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7617378A priority Critical patent/JPS554726A/en
Publication of JPS554726A publication Critical patent/JPS554726A/en
Publication of JPH0239036B2 publication Critical patent/JPH0239036B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To use a fixed head to perform an effecitve recording by forming word date blocks, which are obtained by dividing PCM signals of the same channel, and a parity block for every divided block and adding a CRC code.
CONSTITUTION: PCM signals of the same channel becomes data blocks, which are divided by two, etc., through parallel circuit 2 and time base compression circuits 3 and 4, and a parity block is formed in parity forming circuit 5 by the simple addition and the mode 2 addition of every divided signals, and the parity block following the word block is formed through delay circuit 6, parallel circuit 7, etc., A CRC code generated by CRC generation circuits 8 and 9 is added to these blocks, and data is recorded by multi-fixed heads 17 and 18 of two channels, etc. As a result, PCM signals are distributed and recorded according to the recording density of every track, and added redundant bits for errors such as drop-out restrained to a minimum, so that fixed heads can be used to perform an effective PCM recording.
COPYRIGHT: (C)1980,JPO&Japio
JP7617378A 1978-06-23 1978-06-23 Pcm signal recording method Granted JPS554726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7617378A JPS554726A (en) 1978-06-23 1978-06-23 Pcm signal recording method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7617378A JPS554726A (en) 1978-06-23 1978-06-23 Pcm signal recording method

Publications (2)

Publication Number Publication Date
JPS554726A true JPS554726A (en) 1980-01-14
JPH0239036B2 JPH0239036B2 (en) 1990-09-03

Family

ID=13597691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7617378A Granted JPS554726A (en) 1978-06-23 1978-06-23 Pcm signal recording method

Country Status (1)

Country Link
JP (1) JPS554726A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0420539U (en) * 1990-06-12 1992-02-20
JPH0564342U (en) * 1992-02-10 1993-08-27 ニチハ株式会社 Joint structure of outer wall

Also Published As

Publication number Publication date
JPH0239036B2 (en) 1990-09-03

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