JPS54152903A - Time-division multiple network system - Google Patents
Time-division multiple network systemInfo
- Publication number
- JPS54152903A JPS54152903A JP6202278A JP6202278A JPS54152903A JP S54152903 A JPS54152903 A JP S54152903A JP 6202278 A JP6202278 A JP 6202278A JP 6202278 A JP6202278 A JP 6202278A JP S54152903 A JPS54152903 A JP S54152903A
- Authority
- JP
- Japan
- Prior art keywords
- time
- circuits
- division
- division multiple
- sending
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
- H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
- H04L12/525—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques involving a stored program control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To improve both transmission efficiency and reliability of a system by providing each time-division multiplexer with a sending-address buffer part which controls time slots on time-division mulitple circuits, and by sending transmitting information by finding an idle time slot. CONSTITUTION:This system is provided with channels 4 to 12 connected to node control parts 3-0 to 3-2 and time-division multiple circuits 21 to 26, and port adaptors 13 to 16 connected to terminals 17 to 20, so as to obtain time-division multiple network 1 which links mutually circuits 21 to 26 by time-division multiplexers 2-0 to 2-2. In this network 1, channels 4 to 12 of multiplexers 2-0 to 2-2 are provided with the sending address buffer part which controls time slops on circuits 21 to 26. Then, a transmission request is sent to the buffer part and an idle time slot among time slots is assigned; and each processing mode to send out transmitting information to citcuits 21 to 26 is registered at the time of the assigned time slot and information is sent out by the idle time slot.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53062022A JPS5810021B2 (en) | 1978-05-24 | 1978-05-24 | Time division multiplex network system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53062022A JPS5810021B2 (en) | 1978-05-24 | 1978-05-24 | Time division multiplex network system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54152903A true JPS54152903A (en) | 1979-12-01 |
JPS5810021B2 JPS5810021B2 (en) | 1983-02-23 |
Family
ID=13188121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53062022A Expired JPS5810021B2 (en) | 1978-05-24 | 1978-05-24 | Time division multiplex network system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5810021B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4393381A (en) * | 1981-01-02 | 1983-07-12 | T-Bar Incorporated | Transfer bus matrix |
US4504946A (en) * | 1982-06-11 | 1985-03-12 | Rca Corporation | Time division multiple access communication systems |
JPS61257039A (en) * | 1985-04-03 | 1986-11-14 | シーメンス アクチエンゲゼルシヤフト | Communication controller |
JPS6282737A (en) * | 1985-10-07 | 1987-04-16 | Fujitsu Ltd | Multiplex controller |
JPS63128829A (en) * | 1986-11-18 | 1988-06-01 | Nec Corp | Time slot assignment system |
JPS63202145A (en) * | 1987-02-17 | 1988-08-22 | Nec Corp | Time slot assigning system |
JPS63246057A (en) * | 1987-04-01 | 1988-10-13 | Harada Kogyo Kk | Digital data transmission system |
-
1978
- 1978-05-24 JP JP53062022A patent/JPS5810021B2/en not_active Expired
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4393381A (en) * | 1981-01-02 | 1983-07-12 | T-Bar Incorporated | Transfer bus matrix |
US4504946A (en) * | 1982-06-11 | 1985-03-12 | Rca Corporation | Time division multiple access communication systems |
JPS61257039A (en) * | 1985-04-03 | 1986-11-14 | シーメンス アクチエンゲゼルシヤフト | Communication controller |
JPH0624371B2 (en) * | 1985-04-03 | 1994-03-30 | シーメンス アクチエンゲゼルシヤフト | Communication control device |
JPS6282737A (en) * | 1985-10-07 | 1987-04-16 | Fujitsu Ltd | Multiplex controller |
JPS63128829A (en) * | 1986-11-18 | 1988-06-01 | Nec Corp | Time slot assignment system |
JPS63202145A (en) * | 1987-02-17 | 1988-08-22 | Nec Corp | Time slot assigning system |
JPS63246057A (en) * | 1987-04-01 | 1988-10-13 | Harada Kogyo Kk | Digital data transmission system |
Also Published As
Publication number | Publication date |
---|---|
JPS5810021B2 (en) | 1983-02-23 |
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