JPS54125016A - Medium erasing system - Google Patents

Medium erasing system

Info

Publication number
JPS54125016A
JPS54125016A JP3341578A JP3341578A JPS54125016A JP S54125016 A JPS54125016 A JP S54125016A JP 3341578 A JP3341578 A JP 3341578A JP 3341578 A JP3341578 A JP 3341578A JP S54125016 A JPS54125016 A JP S54125016A
Authority
JP
Japan
Prior art keywords
erase
control circuit
mtucont
value
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3341578A
Other languages
Japanese (ja)
Inventor
Kazuo Kumagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3341578A priority Critical patent/JPS54125016A/en
Publication of JPS54125016A publication Critical patent/JPS54125016A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce program memory regions and make the formation of programs easy by determining the erase range on recording range depending upon the contents of the memory.
CONSTITUTION: The erase command ERSCMD inputted from the channel CH side to the interface control circuit IF.CONT of a controller MTC is stored in a magnetic tape apparatus control circuit MTUCONT and the value of a channel command word CCW in an erase length memory circuit ERSMEM respectively. An erase running instruction is given from the control circuit MTUCONT to a capstan motor M and pulses are generated from a tacho pulse generator TCH according to the number of revolutions of the motor M. The pulses are then counted with an erase length counter ERSCTR. The value having been stored in the erase length memory circuit ERSMEM and the value of the erase length counter ERSCTR are compared in a comparator CMP and when these coincide, a running stop instruction is given to the control circuit MTUCONT.
COPYRIGHT: (C)1979,JPO&Japio
JP3341578A 1978-03-22 1978-03-22 Medium erasing system Pending JPS54125016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3341578A JPS54125016A (en) 1978-03-22 1978-03-22 Medium erasing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3341578A JPS54125016A (en) 1978-03-22 1978-03-22 Medium erasing system

Publications (1)

Publication Number Publication Date
JPS54125016A true JPS54125016A (en) 1979-09-28

Family

ID=12385935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3341578A Pending JPS54125016A (en) 1978-03-22 1978-03-22 Medium erasing system

Country Status (1)

Country Link
JP (1) JPS54125016A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768733B2 (en) 2005-03-18 2010-08-03 Fujitsu Limited Method for erasing data from magnetic tape storage media

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768733B2 (en) 2005-03-18 2010-08-03 Fujitsu Limited Method for erasing data from magnetic tape storage media

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