JPH11504783A - 低電力及び多状態装置における準安定決定時間を向上する回路 - Google Patents
低電力及び多状態装置における準安定決定時間を向上する回路Info
- Publication number
- JPH11504783A JPH11504783A JP9530744A JP53074497A JPH11504783A JP H11504783 A JPH11504783 A JP H11504783A JP 9530744 A JP9530744 A JP 9530744A JP 53074497 A JP53074497 A JP 53074497A JP H11504783 A JPH11504783 A JP H11504783A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- metastable
- coupled
- detecting
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/033—Monostable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.低電力回路における準安定決定時間を向上する回路であって、該低電力回路 は、決議部(Q1、Q2)、データを受信するための入力及び出力を持ち、当該 回路は、この回路における準安定状況を検出するための該低電力回路の前記出力 (A、B)に結合される検出手段(Q5〜Q7)と、前記準安定状況を検出した 場合、前記決議部(Q1、Q2)に供給されるエネルギを局部的に上昇させるた めの前記検出手段(Q5〜Q7)及び該決議部(Q1、Q2)に結合される制御 手段(Q3、Q4)とを有することを特徴とする回路。 2.請求項1に記載の回路において、前記制御手段は、回路供給電圧(Vcc) に結合されるフィードバックチャネリング回路を有し、該チャネリング回路は、 前記供給電圧の上昇分を前記決議部(Q1、Q2)に供給することを特徴とする 回路。 3.請求項1に記載の回路において、前記検出手段は、NORゲート(Q5〜Q 7)を有すること特徴とする回路。 4.請求項1に記載の回路において、前記検出手段は、排他的ORゲート(14 )を有することを特徴とする回路。 5.多状態装置における準安定決定時間を向上する回路であって、該多状態装置 は、決議部、データを受信するための入力及び出力を持ち、当該回路は、この回 路における準安定状況を検出するための前記多状態装置の前記出力に結合される 検出手段と、前記準安定状況を検出した場合、前記決議部に供給されるエネルギ を局部的に上昇させるための前記検出手段及び該決議部に結合される制御手段と を有することを特徴とする回路。 6.請求項5に記載の回路において、前記制御手段は、回路供給電圧に結合され るフィードバックチャネリング回路を有し、該チャネリング回路は、前記供給電 圧の上昇分を前記決議部に供給することを特徴とする回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/607,404 US5789945A (en) | 1996-02-27 | 1996-02-27 | Method and circuit for improving metastable resolving time in low-power multi-state devices |
US08/607,404 | 1996-02-27 | ||
PCT/IB1997/000094 WO1997032398A1 (en) | 1996-02-27 | 1997-02-07 | Circuit for improving metastable resolving time in low-power and multi-state devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11504783A true JPH11504783A (ja) | 1999-04-27 |
JP4469942B2 JP4469942B2 (ja) | 2010-06-02 |
Family
ID=24432118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53074497A Expired - Lifetime JP4469942B2 (ja) | 1996-02-27 | 1997-02-07 | 低電力及び多状態装置における準安定解消時間を向上させる回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5789945A (ja) |
EP (1) | EP0826272B1 (ja) |
JP (1) | JP4469942B2 (ja) |
KR (1) | KR100421578B1 (ja) |
DE (1) | DE69724366T2 (ja) |
WO (1) | WO1997032398A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100304691B1 (ko) * | 1998-05-29 | 2001-09-29 | 윤종용 | 트라이스테이트 보상회로를구비하는 출력신호 발생회로 |
US6369609B1 (en) | 2000-05-08 | 2002-04-09 | Cypress Semiconductor Corp. | Degenerate network for PLD and plane |
US6687864B1 (en) | 2000-06-08 | 2004-02-03 | Cypress Semiconductor Corp. | Macro-cell flip-flop with scan-in input |
US6674306B1 (en) | 2001-06-07 | 2004-01-06 | Cypress Semiconductor Corp. | Multiport arbitration using phased locking arbiters |
US6515517B1 (en) * | 2001-06-07 | 2003-02-04 | Cypress Semiconductor Corp. | Discriminator circuit |
US6826642B1 (en) | 2001-06-07 | 2004-11-30 | Cypress Semiconductor Corp. | Method and apparatus for the use of discriminators for priority arbitration |
US6498513B1 (en) | 2001-06-07 | 2002-12-24 | Cypress Semiconductor Corp. | Metastability recovery circuit |
US6603415B1 (en) * | 2001-07-30 | 2003-08-05 | Cirrus Logic, Inc. | Circuits and methods for latch metastability detection and compensation and systems using the same |
US6531905B1 (en) | 2001-12-19 | 2003-03-11 | Neoaxiom Corporation | Flip-flop with metastability reduction |
GB2468327A (en) * | 2009-03-03 | 2010-09-08 | Icera Inc | A CMOS latch with rapid resolution of a metastable state |
US7977975B1 (en) * | 2009-09-18 | 2011-07-12 | Altera Corporation | Apparatus for using metastability-hardened storage circuits in logic devices and associated methods |
US8289050B2 (en) * | 2010-09-21 | 2012-10-16 | Micron Technology, Inc. | Switching circuits, latches and methods |
US8330517B1 (en) | 2010-12-21 | 2012-12-11 | Xilinx, Inc. | Bistable circuit with metastability resistance |
US8760208B2 (en) | 2012-03-30 | 2014-06-24 | Intel Corporation | Latch with a feedback circuit |
US9252751B2 (en) | 2014-05-04 | 2016-02-02 | Freescale Semiconductor, Inc. | Apparatus and method for preventing multiple resets |
US9329210B1 (en) | 2014-11-29 | 2016-05-03 | Freescale Semiocnductor, Inc. | Voltage monitoring circuit |
US9729129B2 (en) * | 2014-12-05 | 2017-08-08 | Bhaskar Gopalan | System and method for reducing metastability in CMOS flip-flops |
DE102015122907B4 (de) | 2015-12-29 | 2019-07-04 | Infineon Technologies Ag | Speichereinrichtung und Verfahren zum Betreiben einer Speichereinrichtung |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4398105A (en) * | 1981-01-22 | 1983-08-09 | Signetics Corporation | Arbiter circuit |
US5187385A (en) * | 1986-08-29 | 1993-02-16 | Kabushiki Kaisha Toshiba | Latch circuit including filter for metastable prevention |
US4835422A (en) * | 1988-03-14 | 1989-05-30 | North American Philips Corporation | Arbiter circuits with metastable free outputs |
US5014226A (en) * | 1988-09-29 | 1991-05-07 | Lsi Logic Corporation | Method and apparatus for predicting the metastable behavior of logic circuits |
EP0375247B1 (en) * | 1988-12-21 | 1996-02-28 | Texas Instruments Incorporated | Metastable tolerant latch |
US4963772A (en) * | 1989-02-07 | 1990-10-16 | North American Philips Corp., Signetics Div. | Metastable-immune flip-flop arrangement |
US5036221A (en) * | 1989-03-31 | 1991-07-30 | Texas Instruments Incorporated | Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal |
US5001371A (en) * | 1990-06-11 | 1991-03-19 | Motorola, Inc. | Meta-stable free flipflop |
US5081377A (en) * | 1990-09-21 | 1992-01-14 | At&T Bell Laboratories | Latch circuit with reduced metastability |
US5365122A (en) * | 1990-11-09 | 1994-11-15 | Vlsi Technology, Inc. | Meta stable resistant signal detector |
US5489865A (en) * | 1992-02-28 | 1996-02-06 | Media Vision, Inc. | Circuit for filtering asynchronous metastability of cross-coupled logic gates |
US5391935A (en) * | 1993-07-22 | 1995-02-21 | International Business Machines Corporation | Assertive latching flip-flop |
-
1996
- 1996-02-27 US US08/607,404 patent/US5789945A/en not_active Expired - Lifetime
-
1997
- 1997-02-07 EP EP97901217A patent/EP0826272B1/en not_active Expired - Lifetime
- 1997-02-07 WO PCT/IB1997/000094 patent/WO1997032398A1/en active IP Right Grant
- 1997-02-07 JP JP53074497A patent/JP4469942B2/ja not_active Expired - Lifetime
- 1997-02-07 DE DE69724366T patent/DE69724366T2/de not_active Expired - Lifetime
- 1997-02-07 KR KR1019970707599A patent/KR100421578B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO1997032398A1 (en) | 1997-09-04 |
US5789945A (en) | 1998-08-04 |
EP0826272A1 (en) | 1998-03-04 |
DE69724366D1 (de) | 2003-10-02 |
JP4469942B2 (ja) | 2010-06-02 |
EP0826272B1 (en) | 2003-08-27 |
KR100421578B1 (ko) | 2004-05-31 |
KR19990008075A (ko) | 1999-01-25 |
DE69724366T2 (de) | 2004-06-24 |
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