JPH0787199B2 - Head drive IC and head substrate - Google Patents

Head drive IC and head substrate

Info

Publication number
JPH0787199B2
JPH0787199B2 JP3181492A JP3181492A JPH0787199B2 JP H0787199 B2 JPH0787199 B2 JP H0787199B2 JP 3181492 A JP3181492 A JP 3181492A JP 3181492 A JP3181492 A JP 3181492A JP H0787199 B2 JPH0787199 B2 JP H0787199B2
Authority
JP
Japan
Prior art keywords
pads
head
input
pad
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3181492A
Other languages
Japanese (ja)
Other versions
JPH0563022A (en
Inventor
▲隆▼也 長畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP3181492A priority Critical patent/JPH0787199B2/en
Publication of JPH0563022A publication Critical patent/JPH0563022A/en
Publication of JPH0787199B2 publication Critical patent/JPH0787199B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、感熱方式、熱転写方式
のファクシミリやプリンタ等に使用するサーマルヘッ
ド、ＬＥＤヘッド等に実装するヘッド駆動用ＩＣ及び、
ヘッド駆動用ＩＣを搭載したヘッド基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a head driving IC mounted on a thermal head, an LED head or the like used in a thermal type or thermal transfer type facsimile or printer.
The present invention relates to a head substrate on which a head driving IC is mounted.

【０００２】[0002]

【従来の技術】ファクシミリやプリンタ等に使用される
サーマルヘッドの代表例として、サーマルプリントヘッ
ドは、印字走査方向に延在する発熱抵抗体と、抵抗体を
駆動するための駆動用ＩＣと、抵抗体とＩＣを連絡する
ための配線パターンとを有する。サーマルプリントヘッ
ドは、印字ドット数に応じた発熱抵抗体を有し、この抵
抗体を印字ドットパターンに則して駆動するためのデー
タ信号を各抵抗体に送るために、幾つかの抵抗体を一ま
とめにした組数に相当する数のＩＣが設けられる。2. Description of the Related Art As a typical example of a thermal head used in a facsimile, a printer or the like, a thermal print head has a heating resistor extending in a print scanning direction, a driving IC for driving the resistor, and a resistor. It has a wiring pattern for connecting the body and the IC. The thermal print head has a heating resistor corresponding to the number of print dots, and several resistors are provided in order to send a data signal for driving the resistor according to the print dot pattern to each resistor. ICs are provided in a number corresponding to the number of sets combined.

【０００３】この駆動用ＩＣは、一般に図４に示すよう
に、ＩＣ１００上面の１辺の近傍に、発熱抵抗体を駆動
する信号を送り出す全ての出力パッド１０１を配列し
て、出力パッド列１０２とし、対向辺の近傍に入力信号
（データ、クロック、ラッチ、ＧＮＤ、ＶDD、ＳＴＲ等
の信号）を受ける全ての入力パッド１０３を配列して、
入力パッド列１０４としている。In this driving IC, generally, as shown in FIG. 4, all output pads 101 that send out a signal for driving a heating resistor are arranged near one side of the upper surface of the IC 100 to form an output pad row 102. , All input pads 103 for receiving input signals (data, clock, latch, GND, V DD , STR, etc.) are arranged in the vicinity of the opposite side,
The input pad row 104 is used.

【０００４】[0004]

【発明が解決しようとする課題】ところで、殆どのサー
マルプリントヘッドでは、データ、クロック、ラッチ、
ＧＮＤ、ＶDDの信号は各１系統しか使用していないた
め、セラミック基板上又はフレキシブルケーブル上で各
ＩＣの信号を接続している。又、ＳＴＲの信号は数系統
に分割して使用している。By the way, in most thermal print heads, data, clock, latch,
Since only one system is used for each of GND and V DD signals, signals of each IC are connected on a ceramic substrate or a flexible cable. The STR signal is divided into several systems for use.

【０００５】しかしながら、セラミック基板上で上記の
如き駆動用ＩＣの配線接続を行う場合、出力パッドを１
辺寄りに集中配置してあるので、入力信号の配線は他の
対向する一辺側となり、基板上に複雑な配線パターンを
形成したり、多層配線を行ったりする必要がある。それ
ばかりか、ＶDDやＧＮＤの電圧低下を防ぐにはＶDDやＧ
ＮＤに対応する配線パターン幅をできるだけ大きくしな
ければならないが、出力パッドを１辺に偏って配置して
あるので、限られた配線領域内で十分な幅のパターンを
形成するのが困難である。However, when the wiring connection of the driving IC as described above is made on the ceramic substrate, the output pad is set to 1
Since the input signals are concentrated on one side, the wiring for input signals is on the other side facing each other, and it is necessary to form a complicated wiring pattern on the substrate or perform multilayer wiring. Not only that, but to prevent the voltage drop of V DD and GND, V DD and G
Although the wiring pattern width corresponding to ND must be made as large as possible, it is difficult to form a pattern having a sufficient width in a limited wiring region because the output pads are arranged on one side. .

【０００６】又、フレキシブルケーブル上で配線する場
合、セラミック基板との接続部の信号数が多くなるた
め、信頼性の劣化やコスト高につながる。このように、
セラミック基板上の配線とフレキシブルケーブル上の配
線とのパターン抵抗の相違、及びＩＣの使用上必要な信
号系と不要な信号系との関連性を考慮すると、従来の駆
動用ＩＣは通常のセラミック基板又はフレキシブルケー
ブルのどちらかに配線しなければならないのに、実際は
セラミック基板又はフレキシブルケーブル上で殆ど全て
の配線を行っているため、上記電圧低下又は信頼性の劣
化等の問題点が生ずる。Further, when wiring is performed on a flexible cable, the number of signals at the connecting portion with the ceramic substrate increases, which leads to deterioration of reliability and high cost. in this way,
Considering the difference in the pattern resistance between the wiring on the ceramic substrate and the wiring on the flexible cable, and the relationship between the signal system necessary for using the IC and the unnecessary signal system, the conventional driving IC is a normal ceramic substrate. Alternatively, the wiring must be provided on either the flexible cable, but in reality, almost all the wiring is performed on the ceramic substrate or the flexible cable, which causes problems such as the above voltage drop and deterioration of reliability.

【０００７】従って、本発明の目的は、配線パターンを
単純化でき、しかも電圧低下や信頼性の悪化を防ぐこと
ができるヘッド駆動用ＩＣを提供することにある。Therefore, an object of the present invention is to provide a head driving IC which can simplify a wiring pattern and can prevent a voltage drop and deterioration of reliability.

【０００８】[0008]

【課題を解決するための手段】前記目的を達成する本発
明のヘッド駆動用ＩＣは、平面視が四角形のＩＣの上面
において、１辺の近傍にヘッド駆動信号の出力パッドを
配列し、前記辺に直交する別の１辺の近傍に少なくとも
データの入力のパッドを、その対向辺の近傍にデータの
出力パッドを、それぞれ配置し、前記ヘッド駆動用信号
の出力パッドが配列される辺に対向する近傍に他の信号
の入力パッドを配列したことを特徴とする。In a head drive IC of the present invention for achieving the above object, head drive signal output pads are arranged in the vicinity of one side on the upper surface of an IC having a quadrangular shape in plan view, and the side is provided. At least in the vicinity of another side orthogonal to
Place the data input pad near the opposite side of the data
The output pads are respectively arranged, and the input pads for other signals are arranged in the vicinity of the side where the output pads for the head drive signals are arranged.

【０００９】本発明のＩＣは、従来のように全ての出力
パッドをＩＣの１辺付近に配置し、全ての入力パッドを
対向辺付近に配置するのとは異なり、全パッドのうち少
なくともデータの入力パッドを出力パッドが設けられる
辺に直交する１辺付近に配置、その対向辺の近傍にデー
タの出力パッドをそれぞれ配置してある。即ち、従来の
ＩＣでは２辺のみにパッドを配置していたのに対し、本
発明のＩＣでは、制御上必要な信号とパターン抵抗を加
味して信号系を分類し、信号系に応じて、素子列に直交
する他の辺にパッドを分割配置したので、配線パターン
を単純化でき、しかもパターン幅を大きくできる。この
結果、電圧低下が防止され、信頼性も向上する。In the IC of the present invention, unlike the conventional case where all the output pads are arranged near one side of the IC and all the input pads are arranged near the opposite side, a small number of all pads are provided.
If necessary, place the data input pad near one side orthogonal to the side where the output pad is provided, and place the data pad near the opposite side.
The output pads of the data are arranged respectively . That is, in the conventional IC, the pads are arranged only on two sides, whereas in the IC of the present invention, the signal system is classified in consideration of the signal and the pattern resistance required for control, and the signal system is classified according to the signal system. Since the pads are separately arranged on the other side orthogonal to the element row, the wiring pattern can be simplified and the pattern width can be increased. As a result, voltage drop is prevented and reliability is also improved.

【００１０】[0010]

【実施例】以下、本発明のヘッド駆動用ＩＣを実施例に
基づいて説明する。図１はその一実施例のＩＣの平面を
示す。このＩＣ１は、１辺（図中の上辺）の近傍に、６
４ビット分に相当する出力パッド列２が設けられてい
る。出力パッド列２は６４個の出力パッド２１からな
り、出力パッド２１は等間隔を置いて並列する。出力パ
ッド２１は、例えばサーマルプリントヘッドの発熱抵抗
体を駆動する信号を出力するもので、各々の印字出力信
号を対応する発熱抵抗体に送り出す。EXAMPLES A head driving IC of the present invention will be described below based on examples. FIG. 1 shows a plane of an IC of the embodiment. This IC1 has 6 terminals near one side (upper side in the figure).
An output pad row 2 corresponding to 4 bits is provided. The output pad row 2 is composed of 64 output pads 21, and the output pads 21 are arranged in parallel at equal intervals. The output pad 21 outputs, for example, a signal for driving the heating resistor of the thermal print head, and sends each print output signal to the corresponding heating resistor.

【００１１】上辺の対向辺（図中の下辺）の近傍には、
ＧＮＤ、ＶDD、ＳＴＲ信号の入力パッド列３が設けられ
る。入力パッド列３のうち、両端と真中に２個のパッド
を近接して配置した入力パッド３１はＧＮＤで、ＧＮＤ
の間にＶDD信号の入力パッド３２、ＳＴＲ信号の入力パ
ッド３３を配置してある。別の１辺（図中の左辺）の近
傍には、クロック信号の入力パッド４１、データ信号の
入力パッド４２、ラッチ信号の入力パッド４３を順に配
した入力パッド列４を設けてある。この対向辺（図中の
右辺）の近傍には、各入力信号に対応する出力信号の出
力パッド列５が設けられている。クロック信号の入力パ
ッド４１と出力パッド５１、ラッチ信号の入力パッド４
３と出力パッド５３は、それぞれＩＣ１内のパターンで
接続されている。出力パッド列５は、クロック信号の出
力パッド５１、データ信号の出力パッド５２、ラッチ信
号の出力パッド５３からなる。In the vicinity of the opposite side of the upper side (lower side in the figure),
An input pad row 3 for GND, V DD and STR signals is provided. In the input pad row 3, the input pad 31 in which two pads are arranged close to each other at both ends and in the middle is GND.
An input pad 32 for the V DD signal and an input pad 33 for the STR signal are arranged between them. An input pad row 4 in which a clock signal input pad 41, a data signal input pad 42, and a latch signal input pad 43 are arranged in this order is provided near another one side (the left side in the drawing). An output pad row 5 for an output signal corresponding to each input signal is provided near the opposite side (right side in the figure). Clock signal input pad 41 and output pad 51, latch signal input pad 4
3 and the output pad 53 are connected by a pattern in the IC 1. The output pad row 5 includes a clock signal output pad 51, a data signal output pad 52, and a latch signal output pad 53.

【００１２】このようなＩＣでは、ＩＣの左右の辺に１
系統の信号（クロック、データ、ラッチ信号）の入出力
パッドを配置してあるので、この信号系の配線パターン
はＩＣの下側に形成し、各パッドと配線パターン間をワ
イヤボンディングしてもよいし、或いは、隣接するＩＣ
のパッド間をワイヤボンディングしてもよい。又、下辺
（出力パッドの配列される辺に対向する辺）に配した入
力パッド列３におけるパッド間の間隔が十分に大きいた
め、これらのパッドの信号系（ＧＮＤ、ＶDD、ＳＴＲ）
の入力パッドに係る配線パターンを単純化できるだけで
なく、パターンを広幅にすることができる。In such an IC, 1 is provided on the left and right sides of the IC.
Since input / output pads for system signals (clock, data, latch signals) are arranged, a wiring pattern for this signal system may be formed below the IC and wire bonding may be performed between each pad and the wiring pattern. Or adjacent IC
The pads may be wire-bonded. Further, since the spacing between the pads in the input pad row 3 arranged on the lower side (the side facing the side where the output pads are arranged) is sufficiently large, the signal system of these pads (GND, V DD , STR)
In addition to simplifying the wiring pattern related to the input pad, the pattern can be widened.

【００１３】このＩＣ１をサーマルプリントヘッドに実
装する場合、例えば通常のＡ４サイズのヘッド（２００
ＤＰＩ）への適用では、図１に示す６４ビットＩＣを２
７個使用することになる。図２に、ヘッドに実装した場
合の各ＩＣ１の接続形態を説明する図を示す。各（又は
２〜７個の）ＩＣ毎に、入力パッド列３に並ぶＧＮＤ、
ＶDD、ＳＴＲの各パッドをセラミック基板上の対応配線
パターンにワイヤボンディングによって接続し、ＧＮ
Ｄ、ＶDD、ＳＴＲの３信号を各パターンから入力する。When this IC1 is mounted on a thermal print head, for example, a normal A4 size head (200
The DPI) is applied to the 64-bit IC shown in FIG.
I will use 7 pieces. FIG. 2 is a diagram illustrating a connection form of each IC 1 when mounted on the head. GND arranged in the input pad row 3 for each (or 2 to 7) ICs,
Connect each pad of V DD and STR to the corresponding wiring pattern on the ceramic substrate by wire bonding, and
Three signals of D, V DD and STR are input from each pattern.

【００１４】入出力パット列４、５にある他の信号（ク
ロック、データ、ラッチ）のパッドを全ＩＣで１系統に
まとめるために、他の信号系の配線パターンはＩＣ１の
下側において左右方向に平行に形成してあり、このＩＣ
１に対しては各パッドに対応する３本の配線を並列させ
てある。各入出力パッドと配線パターンとの接続は、ワ
イヤボンディングにより行う。又は、図２に示すよう
に、各パッド間を直接ワイヤボンディング６０によって
接続してもよい。或いは、直接ワイヤボンディング６０
の以外にも、各ＩＣとの間にワイヤボンディング用の中
継点を設け、ＩＣ上のパッドからのワイヤを中継点にボ
ンディングし、隣のＩＣの対応パッドからのワイヤも同
じ中継点にボンディングする態様も構わない。In order to combine pads of other signals (clock, data, latch) in the input / output pad rows 4 and 5 into one system for all ICs, wiring patterns of other signal systems are arranged in the left and right direction under the IC1. This IC is formed parallel to
For No. 1, three wires corresponding to each pad are arranged in parallel. The connection between each input / output pad and the wiring pattern is performed by wire bonding. Alternatively, as shown in FIG. 2, the pads may be directly connected by wire bonding 60. Alternatively, direct wire bonding 60
In addition to the above, a relay point for wire bonding is provided between each IC, the wire from the pad on the IC is bonded to the relay point, and the wire from the corresponding pad of the adjacent IC is also bonded to the same relay point. The mode does not matter.

【００１５】ここで、図１に示す６４ビットＩＣの実寸
例を示すと、寸法ａは約５〜６ｍｍで、寸法ｂは約１．
５ｍｍであり、このサイズのＩＣを前記のように配線す
ると、フレキシブルケーブル上でのセラミック基板との
接続部のピッチを２．７ｍｍ程度確保できることにな
る。図３は、この発明の他の実施例を示すＩＣを搭載し
たヘッド基板を示す図である。ここで示すヘッド駆動用
ＩＣ１０は、図２に示したものと相違し、データ、クロ
ック及びラッチ信号用のパッド４１、４２、４３は出力
用パッド列２の配列される辺に直交する辺の１辺（図で
は左側）にのみ、設けられており、この辺に対向する辺
（図では右側）には、データの出力パッド５２のみが設
けられている。この実施例では基板２０の上面に、各Ｉ
Ｃ１０の下面を通り、出力用パッド列２に平行に、クロ
ック、データ、及びラッチ用の配線パターン６１、６３
が形成され、また左端及び右端のＩＣの左側及び右側
と、各ＩＣ間に、ＩＣの各クロック、データ、及びラッ
チ用のパッド４１、４２、４３に対応して中継点（パッ
ド）７１、７２、７３が設けられ、各ＩＣ１０の左側の
中継点７１、７２、７３と、各ＩＣの入力パッド４１、
４２、４３がボンディングワイヤ８１、８２、８３で接
続されている。またデータ出力パッド５２がＩＣ１０の
右側のデータ入力中継点４２に接続されている。このデ
ータ出力パッド５２と次のＩＣ１０のデータ入力パッド
４２とは、直接ボンディングワイヤにより接続されても
よい。Here, as an example of the actual size of the 64-bit IC shown in FIG. 1, the dimension a is about 5 to 6 mm and the dimension b is about 1.
If the IC of this size is wired as described above, the pitch of the connection portion with the ceramic substrate on the flexible cable can be secured at about 2.7 mm. FIG. 3 is a diagram showing a head substrate on which an IC showing another embodiment of the present invention is mounted. The head driving IC 10 shown here is different from that shown in FIG. 2, and the pads 41, 42 and 43 for data, clock and latch signals are one of the sides orthogonal to the side where the output pad row 2 is arranged. It is provided only on the side (left side in the figure), and only the data output pad 52 is provided on the side (right side in the figure) facing this side. In this embodiment, each I is formed on the upper surface of the substrate 20.
Wiring patterns 61, 63 for clock, data, and latch that pass through the lower surface of C10 and are parallel to the output pad row 2
Are formed between the left and right ICs at the left and right ends and the ICs, and relay points (pads) 71 and 72 corresponding to pads 41, 42, and 43 for clocks, data, and latches of the ICs. , 73 are provided, the relay points 71, 72, 73 on the left side of each IC 10 and the input pad 41 of each IC,
42 and 43 are connected by bonding wires 81, 82 and 83. The data output pad 52 is connected to the data input relay point 42 on the right side of the IC 10. The data output pad 52 and the data input pad 42 of the next IC 10 may be directly connected by a bonding wire.

【００１６】この実施例ＩＣはクロック及びラッチ信号
用の入力と出力の内部配線が不要である。This embodiment IC does not require internal wiring for input and output for clock and latch signals.

【００１７】[0017]

【発明の効果】本発明のヘッド駆動用ＩＣは、以上説明
したように、平面視が四角形のＩＣの上面において、１
辺の近傍にヘッド駆動信号の出力パッドを配列し、前記
辺に直交する別の１辺の近傍に少なくともデータの入力
パッドをその対向辺の近傍にデータの出力パッドをそれ
ぞれ配置し、前記ヘッド駆動用信号の出力パッドが配列
される辺に対向する辺の近傍に他の信号の入力パッドを
配列したので、ＩＣをヘッドに実装する際にセラミック
基板の配線パターンを単純化若しくは削減でき、しかも
パターン幅を広くしてパターン抵抗を低く抑えることが
できる。このため、電圧低下が防止され、高い信頼性が
得られ、コストも安くなる。As described above, the head drive IC according to the present invention has the following structure:
Head drive signal output pads are arranged in the vicinity of a side, at least a data input pad is arranged in the vicinity of another side orthogonal to the side, and a data output pad is arranged in the vicinity of the opposite side.
Since the input pads for the other signals are arranged in the vicinity of the side opposite to the side where the output pads for the head drive signals are arranged, the wiring pattern of the ceramic substrate is set when the IC is mounted on the head. It can be simplified or reduced, and the pattern resistance can be suppressed low by widening the pattern width. Therefore, voltage drop is prevented, high reliability is obtained, and cost is reduced.

【００１８】又、ユーザーのカスタム要求に幅広く対応
できる。It is also possible to meet a wide range of user custom requirements.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例に係るヘッド駆動用ＩＣの平
面図である。FIG. 1 is a plan view of a head driving IC according to an embodiment of the present invention.

【図２】図１のＩＣをサーマルプリントヘッドに実装す
る場合において、各ＩＣの接続形態を説明するための図
である。FIG. 2 is a diagram for explaining a connection form of each IC when the IC of FIG. 1 is mounted on a thermal print head.

【図３】この発明の他の実施例に係るヘッド駆動用ＩＣ
の実装例及びその接続形態を説明するための図である。FIG. 3 is a head drive IC according to another embodiment of the present invention.
FIG. 3 is a diagram for explaining an implementation example of and the connection form thereof.

【図４】従来の一般的なヘッド駆動用ＩＣの平面図であ
る。FIG. 4 is a plan view of a conventional general head driving IC.

【符号の説明】[Explanation of symbols]

１、１０ ヘッド駆動用ＩＣ ２ ヘッド駆動信号の出力パッド列 ３ ＧＮＤ、ＶDD、ＳＴＲ信号の入力パッド
列 ４ クロック、データ、ラッチ信号の入力パ
ッド列 ５ クロック、データ、ラッチ信号の出力パ
ッド列1, 10 head driving IC 2 head drive signal output pad row 3 GND, V DD , STR signal input pad row 4 clock, data, latch signal input pad row 5 clock, data, latch signal output pad row

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/04 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 27/04

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】平面視が四角形のＩＣの上面において、１
辺の近傍にヘッド駆動信号の出力パッドを配列し、前記
辺に直交する別の１辺の近傍に少なくともデータの入力
パッドを、その対向辺の近傍にデータの出力パッドを、
それぞれ配置し、前記ヘッド駆動用信号の出力パッドが
配列される辺に対向する辺の近傍に他の信号の入力パッ
ドを配列したことを特徴とするヘッド駆動用ＩＣ。1. On an upper surface of an IC having a quadrangular shape in plan view, 1
Head drive signal output pads are arranged near the side, and at least data is input near another side orthogonal to the side.
Pad, data output pad near the opposite side,
A head driving IC, wherein the head driving ICs are arranged respectively , and input pads for other signals are arranged in the vicinity of a side opposite to a side where the output pads for the head driving signals are arranged. 【請求項２】平面視が四角形のＩＣの上面において、１
辺の近傍にヘッド駆動信号の出力パッドを配列し、前記
辺に直交する別の１辺の近傍にデータ、クロック及びラ
ッチ信号用のパッドを、前記ヘッド駆動用信号の出力パ
ッドが配列される辺に対向する辺の近傍に残りの信号の
入力パッドを配列したことを特徴とするヘッド駆動用Ｉ
Ｃ。2. On an upper surface of an IC whose plan view is a quadrangle, 1
Arranging output pads of the head drive signals in the vicinity of the edge, the data in the vicinity of another one side perpendicular to the sides, the pad for a clock and latch signal, an output path of the head drive signals
A head driving I characterized in that input pads for the remaining signals are arranged in the vicinity of a side opposite to the side in which the pads are arranged.
C. 【請求項３】平面視が四角形のＩＣの上面において、１
辺の近傍にヘッド駆動信号の出力パッドを配列し、前記
辺に直交する別の１辺の近傍にデータ、クロック及びラ
ッチ信号の入力パッドを、その対向辺の近傍にこれらの
信号の出力パッドを配列し、残りの辺の近傍に残りの信
号の入力パッドを配列したことを特徴とするヘッド駆動
用ＩＣ。 3. On an upper surface of an IC having a quadrangular shape in plan view, 1
Arrange the output pad of the head drive signal near the side,
The data, clock, and
The input pad of the switch signal near these opposite sides.
Arrange the signal output pads so that the remaining signals are near the remaining edges.
Head drive characterized by arranging the input pads of
IC. 【請求項４】駆動すべき素子列に平行に、複数個の平面
視が四角形の駆動用ＩＣが基板上に搭載されるヘッド基
板において、駆動用ＩＣは、１辺の近傍にヘッド素子駆
動信号の出力パッドを配列し、前記辺に直交する別の一
方の近傍に、データ、クロック、及びラッチ信号の入力
パッドを、前記ヘッド素子駆動信号の出力パッドが配列
される辺に対向する辺の近傍に残りの入力信号のパッド
を配列するものであり、前記データ、クロック、及びラ
ッチ信号の入力パッドの近傍の基板上面に、これら入力
パッドに対向するパッドを形成し、これら基板上のパッ
ド間を個別に結ぶ配線パターンを形成し、前記ＩＣのデ
ータ、クロック、及び、ラッチ信号用の入力パッドと基
板の対応するパッドをボンディングワイヤで接続したこ
とを特徴とするヘッド基板。4. A plurality of planes parallel to a row of elements to be driven.
Head base on which a driving IC having a quadrangle is mounted on a substrate
In the plate, the driving IC is a head element drive near one side.
Another array of the output pads for the motion signal, which is orthogonal to the side.
Input of data, clock, and latch signals near one side
Output pads for the head element drive signals are arranged
Input signal pad near the side opposite the
For arranging the data, clock, and
On the top surface of the board near the input pads for
Form pads that face the pads and use the pads on these substrates.
A wiring pattern that individually connects the
Input pad and base for data, clock and latch signals
Make sure that the corresponding pads on the board are connected with bonding wires.
And a head substrate.
JP3181492A 1991-03-29 1992-02-19 Head drive IC and head substrate Expired - Fee Related JPH0787199B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3181492A JPH0787199B2 (en) 1991-03-29 1992-02-19 Head drive IC and head substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3-66228 1991-03-29
JP6622891 1991-03-29
JP3181492A JPH0787199B2 (en) 1991-03-29 1992-02-19 Head drive IC and head substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP8217229A Division JPH0924635A (en) 1996-08-19 1996-08-19 Thermal print head

Publications (2)

Publication Number Publication Date
JPH0563022A JPH0563022A (en) 1993-03-12
JPH0787199B2 true JPH0787199B2 (en) 1995-09-20

Family

ID=26370325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3181492A Expired - Fee Related JPH0787199B2 (en) 1991-03-29 1992-02-19 Head drive IC and head substrate

Country Status (1)

Country Link
JP (1) JPH0787199B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3908401B2 (en) 1998-12-22 2007-04-25 ローム株式会社 Drive IC chip for print head and print head having the same
JP3573150B2 (en) 2002-01-25 2004-10-06 セイコーエプソン株式会社 Semiconductor device and electro-optical device including the same
JP5375198B2 (en) * 2008-03-07 2013-12-25 セイコーエプソン株式会社 Head substrate and thermal head substrate
KR20200109756A (en) * 2019-03-14 2020-09-23 에스케이하이닉스 주식회사 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230873A (en) * 1984-04-30 1985-11-16 Kyocera Corp Thermal printer
JPS627568A (en) * 1985-07-03 1987-01-14 Nec Corp Thermal head
JPS6392467A (en) * 1986-10-08 1988-04-22 Nec Corp Driving integrated circuit for thermal head
JPH03230964A (en) * 1990-02-06 1991-10-14 Kyocera Corp Thermal head

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6467361A (en) * 1987-09-08 1989-03-14 Nec Corp Thermal head

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230873A (en) * 1984-04-30 1985-11-16 Kyocera Corp Thermal printer
JPS627568A (en) * 1985-07-03 1987-01-14 Nec Corp Thermal head
JPS6392467A (en) * 1986-10-08 1988-04-22 Nec Corp Driving integrated circuit for thermal head
JPH03230964A (en) * 1990-02-06 1991-10-14 Kyocera Corp Thermal head

Also Published As

Publication number Publication date
JPH0563022A (en) 1993-03-12

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