JPH069519Y2 - High frequency circuit mounting structure - Google Patents
High frequency circuit mounting structureInfo
- Publication number
- JPH069519Y2 JPH069519Y2 JP15064387U JP15064387U JPH069519Y2 JP H069519 Y2 JPH069519 Y2 JP H069519Y2 JP 15064387 U JP15064387 U JP 15064387U JP 15064387 U JP15064387 U JP 15064387U JP H069519 Y2 JPH069519 Y2 JP H069519Y2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- integrated circuit
- mounting structure
- soldered
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Landscapes
- Waveguide Connection Structure (AREA)
- Waveguides (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 この考案は高周波集積回路素子と電子回路素子を気密封
止用ケース内に実装される高周波回路の実装構造に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a mounting structure of a high frequency circuit in which a high frequency integrated circuit device and an electronic circuit device are mounted in a hermetically sealed case.
第２図は従来の高周波回路の実装構造を示す図であり，
図において(1a)〜(1c)は誘電体基板上に高周波回路が形
成された高周波集積回路素子，(2)はコンデンサ素子，
(3)は誘電体基板(1a)〜(1c)と同等の線膨張率を有する
金属でできた気密封止用ケース，(4a)は気密封止用ケー
ス(3)に具備された高周波信号用の入出力端子，(4b)は
バイアス線路用の接続端子，(5)は高周波集積回路素子
(1a)〜(1c)やコンデンサ素子(2)等の回路素子間を接続
するワイヤ，(6)は気密封止用ケースのカバーである。FIG. 2 is a diagram showing a conventional high-frequency circuit mounting structure,
In the figure, (1a) to (1c) are high-frequency integrated circuit elements in which a high-frequency circuit is formed on a dielectric substrate, (2) is a capacitor element,
(3) is a hermetically sealed case made of metal having a linear expansion coefficient equivalent to that of the dielectric substrates (1a) to (1c), and (4a) is a high frequency signal provided in the hermetically sealed case (3). Input / output terminal, (4b) connection terminal for bias line, (5) high frequency integrated circuit element
Wires (1a) to (1c) and wires connecting circuit elements such as capacitor element (2), and (6) are covers for the hermetically sealed case.
従来の高周波回路の実装構造は上記のように構成され，
高周波集積回路素子(1a)〜(1c)は気密封止用ケース(3)
内に半田付けされコンデンサ素子(2)は高周波集積回路
素子(1a)〜(1c)の近くに半田付けされる。高周波集積回
路素子(1a)〜(1c)やコンデンサ素子(2)また接続端子(4
a)(4b)間の接続はワイヤ(5)によって行なわれる。The conventional high-frequency circuit mounting structure is configured as described above,
High-frequency integrated circuit devices (1a) to (1c) are hermetically sealed cases (3)
The capacitor element (2) soldered inside is soldered near the high frequency integrated circuit elements (1a) to (1c). High frequency integrated circuit devices (1a) to (1c), capacitor devices (2) and connection terminals (4
The connection between a) and (4b) is made by a wire (5).
各バイアス線路は高周波信号がバイアス線路を通って外
部または他の高周波回路に漏れ出ないようにコンデンサ
素子(2)を介してバイアス線路用接続端子(4b)から高周
波集積回路素子(1a)〜(1c)に接続されている。Each bias line is connected to the bias line connection terminal (4b) via the capacitor element (2) from the high frequency integrated circuit device (1a) to () so that high frequency signals do not leak to the outside or other high frequency circuits through the bias line. It is connected to 1c).
コンデンサ素子(2)は上下の面が電極となっており，上
面にバイアス線路のワイヤ(5)がボンディングされ，下
面は気密封止用ケース(3)に半田付けされ，バイアス線
路の高周波フィルタの役割をはたしている。The upper and lower surfaces of the capacitor element (2) are electrodes, the wire (5) of the bias line is bonded to the upper surface, and the lower surface is soldered to the hermetically sealed case (3). It plays a role.
気密封止用ケース(3)にカバー(6)を被せ，接合面を半田
付けまたは溶接によって気密封止される。The case (3) for hermetic sealing is covered with the cover (6), and the joint surface is hermetically sealed by soldering or welding.
上記のような従来の高周波回路の実装構造では高周波集
積回路素子(1a)〜(1c)の半田付けの際に半田層内に止じ
込められた空気を除去するためのすり合わせをする周囲
のすき間が必要であり，コンデンサ素子(2)は高周波集
積回路素子(1a)〜(1c)の半田付後その周囲に半田付けさ
れる。そのため高周波集積回路素子(1a)〜(1c)は数多く
のコンデンサ素子(2)の半田付け時にも長時間加熱され
るため，高周波集積回路素子(1a)〜(1c)内の半導体部の
損傷や品質劣化を招くおそれがあり，高周波集積回路素
子(1a)〜(1c)への加熱時間を短縮する必要があった。In the conventional high-frequency circuit mounting structure as described above, when the high-frequency integrated circuit elements (1a) to (1c) are soldered, a clearance is created around the solder layer to remove air trapped in the solder layer. The capacitor element (2) is soldered around the high frequency integrated circuit elements (1a) to (1c) after soldering. Therefore, the high-frequency integrated circuit elements (1a) to (1c) are heated for a long time even when many capacitor elements (2) are soldered, and the semiconductor parts in the high-frequency integrated circuit elements (1a) to (1c) are not damaged or damaged. There is a risk of quality deterioration, and it was necessary to shorten the heating time for the high-frequency integrated circuit elements (1a) to (1c).
また，高周波回路素子の厚みがコンデンサ素子等の厚み
より大きい場合には，素子間に段差が生じるため高周波
回路素子とコンデンサ素子等間を結線するためのワイヤ
ボンディング時の作業性が悪くなる。更に，素子間の段
差に伴い，ボンデイングワイヤ長が増大しそのインダク
タンス成分が高周波回路素子の特性に影響するなどの問
題があった。If the thickness of the high-frequency circuit element is larger than that of the capacitor element or the like, a step is generated between the elements, which deteriorates workability during wire bonding for connecting the high-frequency circuit element and the capacitor element or the like. Furthermore, there is a problem that the bonding wire length increases with the step difference between the elements, and the inductance component affects the characteristics of the high-frequency circuit element.
この考案は上記のような問題点を解消するためになされ
たもので数多くのコンデンサ素子等を高周波集積回路素
子の近傍に短時間で半田付けができる高周波回路の実装
構造を得ることを目的とする。The present invention has been made in order to solve the above problems, and an object thereof is to obtain a mounting structure of a high frequency circuit capable of soldering a large number of capacitor elements and the like in the vicinity of the high frequency integrated circuit element in a short time. .
この考案における高周波回路の実装構造は複数のコンデ
ンサ素子等を導体片上に半田付けしたのち，この導体片
を気密封止用ケース上の高周波集積回路素子の近傍に半
田付けしたものである。The high-frequency circuit mounting structure according to the present invention is such that a plurality of capacitor elements and the like are soldered on a conductor piece and then the conductor pieces are soldered on the hermetically sealed case in the vicinity of the high-frequency integrated circuit element.
この考案においては，複数のコンデンサ素子等を気密封
止用ケースとは独立した導体片に予め半田付けしそれを
気密封止用ケースに半田付けするため高周波集積回路素
子が取付けられた気密封止用ケースをコンデンサ素子等
の半田付けのために加熱する時間が大巾に短縮され高周
波集積回路素子に与える影響を緩和する。In this invention, a plurality of capacitor elements and the like are previously soldered to a conductor piece independent of the hermetically sealed case, and the high frequency integrated circuit element is attached to the hermetically sealed case so as to be soldered to the hermetically sealed case. The time for heating the case for soldering the capacitor element or the like is greatly shortened and the influence on the high frequency integrated circuit element is mitigated.
また，高周波回路素子とコンデンサ素子等の厚みが異な
る場合でも，前記導体片の厚みを変えることによって各
素子の高さをほぼ同じにでき，ワイヤボンディング時の
作業性が向上する。更に，ボンディングワイヤ長の増大
をもたらすことなく，高周波特性に優れた高周波回路素
子の実装構造を提供できる。Even when the high-frequency circuit element and the capacitor element have different thicknesses, the height of each element can be made substantially the same by changing the thickness of the conductor piece, and the workability during wire bonding is improved. Furthermore, it is possible to provide a mounting structure of a high-frequency circuit element having excellent high-frequency characteristics without increasing the bonding wire length.
第１図はこの考案の一実施例を示す図であり，(1)〜(6)
は上記従来装置と全く同一のものである。(7)は複数の
コンデンサ素子(2)を上面に半田付けするための導体片
でありコンデンサ素子(2)を半田付けした後，気密封止
用ケース(1)内に半田付けされる。FIG. 1 is a diagram showing an embodiment of the present invention, which is (1) to (6)
Is exactly the same as the above conventional device. Reference numeral (7) is a conductor piece for soldering a plurality of capacitor elements (2) to the upper surface, and after the capacitor elements (2) are soldered, they are soldered in the hermetically sealed case (1).
上記のように構成された高周波回路の実装構造において
は複数のコンデンサ素子(2)が予め半田付けされた導体
片(7)を，気密封止用ケース(3)に半田付けするため気密
封止用ケース(3)を加熱する時間が大巾に短縮されるの
で高周波集積回路素子に与える影響を緩和することにな
る。In the high-frequency circuit mounting structure configured as described above, the conductor piece (7) to which the plurality of capacitor elements (2) are previously soldered is hermetically sealed to be soldered to the hermetically sealing case (3). Since the time for heating the case (3) is greatly shortened, the influence on the high frequency integrated circuit element will be alleviated.
この考案は以上説明したとおり，導体片に複数のコンデ
ンサ素子を半田付けし，それを気密封止用ケースに取付
けるという簡単な構造により，コンデンサ素子を直接気
密封止用ケースに半田付けするよりも気密封止用ケース
を加熱時間が大巾に短縮され，気密封止用ケース内の高
周波集積回路素子の加熱による損傷や品質の劣化を防止
できる効果がある。As described above, this device has a simple structure in which a plurality of capacitor elements are soldered to a conductor piece and attached to the hermetically sealed case, so that the capacitor element is not directly soldered to the hermetically sealed case. The heating time of the hermetically sealed case is greatly shortened, which has the effect of preventing damage to the high-frequency integrated circuit element in the hermetically sealed case and deterioration of its quality.
また、高周波回路素子とコンデンサ素子等の厚みが異な
る場合でも，前記導体片の厚みを変えることによって各
素子の高さをほぼ同じにでき，ワイヤボンディング時の
作業性が向上する。更に，ボンディングワイヤ長の増大
をもたらすことなく，高周波特性に優れた高周波回路素
子の実装構造を提供できる等の多大なる効果がある。Even when the high frequency circuit element and the capacitor element have different thicknesses, the height of each element can be made substantially the same by changing the thickness of the conductor piece, and the workability at the time of wire bonding is improved. Further, there is a great effect that a mounting structure of a high-frequency circuit element having excellent high-frequency characteristics can be provided without increasing the bonding wire length.
本実施例においては，コンデンサ素子等を導体片に取り
つける際半田付けによって説明したが，半田より高い温
度で溶融するＡｕＳｎ等の共晶合金を用いる場合には，
半田付けによる場合より本考案の効果はより大となるこ
とは言うまでもない。In this embodiment, soldering was used to attach the capacitor element and the like to the conductor piece. However, when a eutectic alloy such as AuSn that melts at a higher temperature than the solder is used,
It goes without saying that the effect of the present invention is greater than the case of soldering.
第１図はこの考案の一実施例の高周波回路の実装構造を
示す図，第２図は従来の高周波回路の実装構造を示す図
である。 図において(1a)〜(1c)は高周波集積回路素子，(2)はコ
ンデンサ素子，(3)は気密封止用ケース，(4a)は高周波
信号用接続端子，(4b)はバイアス線路用端子，(5)はワ
イヤ，(6)はカバー，(7)は導体片である。 なお，各図中同一符号は同一または相当部分を示す。FIG. 1 is a diagram showing a mounting structure of a high frequency circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a mounting structure of a conventional high frequency circuit. In the figure, (1a) to (1c) are high-frequency integrated circuit elements, (2) is a capacitor element, (3) is a hermetically sealed case, (4a) is a high-frequency signal connection terminal, and (4b) is a bias line terminal. , (5) is a wire, (6) is a cover, and (7) is a conductor piece. The same reference numerals in each figure indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (72)考案者 原田 洋 神奈川県鎌倉市上町屋325番地 三菱電機 株式会社鎌倉製作所内 (56)参考文献 特公 昭60−43018（ＪＰ，Ｂ２) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Harada 325 Kamimachiya, Kamakura-shi, Kanagawa Mitsubishi Electric Corporation Kamakura Factory (56) References Japanese Patent Publication Sho 60-43018 (JP, B2)
Claims (1)
高周波集積回路素子と，上記高周波集積回路素子を収納
する気密封止用ケースと，高周波回路用バイアス線路へ
の高周波信号の漏れを阻止するコンデンサ素子等とを具
備し，上記高周波集積回路素子と上記コンデンサ素子等
をワイヤボンディングで接続した高周波回路の実装構造
において，複数の上記コンデンサ素子を予め半田付けし
た導体片を上記気密封止用ケース内に半田付けしたこと
を特徴とする高周波回路の実装構造。1. A high-frequency integrated circuit device having a high-frequency circuit formed on a dielectric substrate, a hermetically sealed case for housing the high-frequency integrated circuit device, and a high-frequency circuit bias line for preventing leakage of a high-frequency signal. In a mounting structure of a high frequency circuit in which the high frequency integrated circuit element and the capacitor element are connected by wire bonding, a conductor piece to which a plurality of the capacitor elements are soldered in advance is used for the hermetic sealing. A high-frequency circuit mounting structure characterized by being soldered in a case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15064387U JPH069519Y2 (en) | 1987-10-01 | 1987-10-01 | High frequency circuit mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15064387U JPH069519Y2 (en) | 1987-10-01 | 1987-10-01 | High frequency circuit mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6457657U JPS6457657U (en) | 1989-04-10 |
| JPH069519Y2 true JPH069519Y2 (en) | 1994-03-09 |
Family
ID=31423970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15064387U Expired - Lifetime JPH069519Y2 (en) | 1987-10-01 | 1987-10-01 | High frequency circuit mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH069519Y2 (en) |
-
1987
- 1987-10-01 JP JP15064387U patent/JPH069519Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6457657U (en) | 1989-04-10 |
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