JPH0468560A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0468560A JPH0468560A JP18053590A JP18053590A JPH0468560A JP H0468560 A JPH0468560 A JP H0468560A JP 18053590 A JP18053590 A JP 18053590A JP 18053590 A JP18053590 A JP 18053590A JP H0468560 A JPH0468560 A JP H0468560A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip mounting
- lead
- wire
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000605 extraction Methods 0.000 claims description 14
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は小型面実装素子として好適する半導体装置に関
するもので、特に超小型パッケージ内に多大の機能を盛
込む為にチップの搭載能力を拡大したい場合に使用する
ものである。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device suitable as a small surface-mounted device, and particularly to a semiconductor device suitable for incorporating a large number of functions into an ultra-small package. This is used when you want to expand the loading capacity of the aircraft.
（従来の技術）
従来技術による半導体装置のリードフレームの平面図を
第５図（ａ）に、同断面図を第５図（ｂ）に示す。この
リードフレームは、チップ搭載部１１と、リード引出し
電極部１２がパンチングによって打抜かれ、独立した部
分に分割されている。(Prior Art) A plan view of a lead frame of a semiconductor device according to the prior art is shown in FIG. 5(a), and a cross-sectional view thereof is shown in FIG. 5(b). This lead frame is divided into independent parts by punching a chip mounting part 11 and a lead extraction electrode part 12.
第５図中１３はチップ搭載部とリード引出し電極部の分
離ギャップ、１４は半導体チップ、１５はリードワイヤ
ー（ボンディングワイヤー）、１６はモールド体（パッ
ケージ）、１７はリードワイヤーとチップのエツジとの
ギャップである。In Fig. 5, 13 is the separation gap between the chip mounting part and the lead extraction electrode part, 14 is the semiconductor chip, 15 is the lead wire (bonding wire), 16 is the mold body (package), and 17 is the separation gap between the lead wire and the edge of the chip. It's a gap.
（発明が解決しようとする課題）
ところで近時、電子機器の小型、軽量化の進展に伴い、
半導体装置も小型化、超小型化か急進している。この半
導体装置を、電子機器を構成する基板へ実装する場合、
実装密度を上げる為にパッケージはリードタイプから表
面実装タイプ（以下Ｓｕ＋４ａｃｅ Ｍｏｕｎｔ Ｄｅ
ｖｉｃｅ −Ｓ Ｍ Ｄと略す）に移行している。(Problem to be solved by the invention) Recently, with the progress of electronic devices becoming smaller and lighter,
Semiconductor devices are also rapidly becoming smaller and more miniaturized. When mounting this semiconductor device on a board that constitutes an electronic device,
In order to increase the packaging density, the package has changed from the lead type to the surface mount type (hereinafter referred to as Su+4ace Mount De
vice-SMD).
高密度実装の極限として、半導体チップそのものを基板
に実装する方法もあるが、ワイヤボンディングか必要で
あるとか、表面保護とかの問題も多い。従ってＳＭＤ構
造でかつ超小型、高性能の半導体装置を実現する為には
、ＳＭＤのバソケジ内に最大限のチップを搭載する必要
がある。At the extreme of high-density packaging, there is a method of mounting the semiconductor chip itself on the board, but this requires wire bonding and has many problems such as surface protection. Therefore, in order to realize an ultra-small, high-performance semiconductor device with an SMD structure, it is necessary to mount as many chips as possible in the SMD cage.
従来のＳＭＤに使用されるリードフレームは第５図（ａ
、 ）に示す如く、パンチングによってチップ搭載部１
１とリード電極引出し部１２に分離され、この時、υ−
ト材厚に相当するギャップ１３を設ける必要がある。The lead frame used in conventional SMD is shown in Figure 5 (a
, ), the chip mounting area 1 is removed by punching.
1 and lead electrode extraction part 12, at this time, υ-
It is necessary to provide a gap 13 corresponding to the thickness of the material.
このギャップ１３はリードフレームの材質によって異な
るが、リードフレームを精度良く、安定にパンチングす
るのに必要な刃の強度を確保する刃の厚さに相当するも
のである。This gap 13 varies depending on the material of the lead frame, but corresponds to the thickness of the blade that ensures the strength of the blade necessary to punch the lead frame accurately and stably.
従ってこの刃の厚さには限界があり、パッケージ１６が
小さくなるにつれて、これらのギャップ１３の部分の占
める割合は増大し、逆にチップ搭載部１１の面積は相対
的に小さくなる欠点がある。Therefore, there is a limit to the thickness of this blade, and as the package 16 becomes smaller, the ratio occupied by the gap 13 increases, and conversely, the area of the chip mounting portion 11 becomes relatively smaller.
更に第５図（ｂ）に示す如く、パッケージ１６か小さく
なり、前述のギャップ１３が狭くなる程、チップ］４の
エツジとリードワイヤー１５とのギャップ］７も狭くな
り、双方がタッチする危険性か増大する欠点かある。Furthermore, as shown in FIG. 5(b), as the package 16 becomes smaller and the aforementioned gap 13 becomes narrower, the gap between the edge of the chip 4 and the lead wire 15 7 also becomes narrower, increasing the risk of the two touching. Or is there an increasing drawback?
上記のように、電子機器の小型化に対応した表面実装素
子（Ｓ Ｍ Ｄ ）の高機能化に当って、より多くの機
能を持った大きなチップサイズのチップを搭載する必要
がある。As described above, in order to improve the functionality of surface mount devices (SMD) that correspond to the miniaturization of electronic devices, it is necessary to mount a large chip size chip with more functions.
これは内蔵するチップの微細化が進めば、それによる余
裕は更に機能増加に利用され、より小さＬ）Ｓ Ｍ Ｄ
に、より大きなチップを搭載することが追求される。こ
の為にＳＭＤ内部のリードフレーム構造において、最大
限のチップ搭載部の面積を確保する必要かある。This is because as the built-in chip becomes smaller, the resulting margin will be used to further increase functionality, making it smaller L) S M D
Equipped with larger chips is being pursued. For this reason, it is necessary to secure the maximum area for the chip mounting portion in the lead frame structure inside the SMD.
そこで本発明の目的は、チップ搭載部の面積は極めて大
きく確保でき、またチップのエツジとリードワイヤーと
の接近による接触を防止することにある。SUMMARY OF THE INVENTION An object of the present invention is to ensure an extremely large area for the chip mounting portion and to prevent the edges of the chip from coming into contact with the lead wires due to their proximity.
口発明の構成〕
（課題を解決するための手段と作用）
本発明は、チップ搭載部とリード引出し電極の端部が、
平面的に見て同一切断面となり、前記チップ搭載部のチ
ップ搭載面とリード引出し電極面か、側面的に見て同一
平面上になく上下にずらした事を特徴とする半導体装置
である。Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides that the chip mounting portion and the end of the lead extraction electrode are
The semiconductor device is characterized in that the cut planes are the same when viewed from above, and the chip mounting surface of the chip mounting portion and the lead extraction electrode surface are not on the same plane when viewed from the side, but are shifted vertically.
即ち本発明は、リードフレームの形成に当って、チップ
搭載部とリード引出し電極部を、平面的に見て一体化形
状に、つまり双方が離間していないかの如くパンチング
する。またリード引出し部は、せん断にて一体化形状部
より分離する。またチップ搭載部に連続する部分または
り一ト引出し電極部は、所定の位置へ変形させることに
よって相互に面をずらすのみとして、従来パンチングに
て除去していた部分をチップ搭載部として活用するもの
である。また上記双方の面をずらすことで、チップのエ
ツジとリードワイヤーとが極力離れるようにして、これ
ら双方が接触しに＜＜シたものである。That is, in the present invention, when forming a lead frame, the chip mounting part and the lead extraction electrode part are punched into an integrated shape when viewed from above, that is, as if they were not separated from each other. Further, the lead pull-out portion is separated from the integrated shape portion by shearing. In addition, the part that is continuous with the chip mounting part or the lead-out electrode part is simply deformed to a predetermined position so that the surfaces of the parts are shifted from each other, and the part that was conventionally removed by punching is utilized as the chip mounting part. It is. In addition, by shifting the two surfaces, the edge of the chip and the lead wire are kept as far apart as possible to prevent them from coming into contact with each other.
（実施例）
以下図面を参照して本発明の一実施例を説明する。第１
図（ａ）は同実施例の平面図、同図（ｂ）は同断面図で
あるが、これは第５図のものと対応させた場合の例であ
るから、対応する個所には同一符号を用い、特徴とする
点の説明を行なう。第１図の特徴は、チップ搭載部１１
とリード引出し電極１２の端部が、平面的に見て同一切
断面１８となり、チップ搭載部１１のチップ搭載面とリ
ート引出し電極１２の面が、側面的に見て同一平面上に
なく、上下にすれていることである。(Example) An example of the present invention will be described below with reference to the drawings. 1st
Figure (a) is a plan view of the same embodiment, and Figure (b) is a cross-sectional view of the same example, but since this is an example in which it corresponds to that in Figure 5, corresponding parts are denoted by the same reference numerals. We will use this to explain the features. The feature of FIG. 1 is that the chip mounting section 11
The end of the lead extraction electrode 12 becomes the same cut surface 18 when viewed from above, and the chip mounting surface of the chip mounting portion 11 and the surface of the lead extraction electrode 12 are not on the same plane when viewed from the side, but are vertically aligned. It is something that has become familiar to me.
第１図のような構成であれば、第５図の分離ギヤツブ１
３か無い分たけ第１図のチップ搭載部１１の面積を広く
とれる。またチップ搭載面が電極１２の面より下にすれ
ていることで、ワイヤ１５とチップ１４のエツジとのギ
ャップ１７が大となり、双方が接触しにくくなるし、ま
たワイヤー１５の長さを極力短くすることができる。If the configuration is as shown in Figure 1, the separation gear 1 in Figure 5
The area of the chip mounting portion 11 shown in FIG. 1 can be increased to the extent that there are no 3 or 3 chips. Furthermore, since the chip mounting surface is sliding below the surface of the electrode 12, the gap 17 between the wire 15 and the edge of the chip 14 becomes large, making it difficult for them to come into contact with each other. can do.
上記構成を得るには、第３図（ａ）で、ます、リードフ
レームの原材をパンチングし、チップ搭載部とリード引
出し電極部が一体のリードフレーム３１を得る。次に第
３図（ｂ）の如く、チップ搭載部１］とリード引出し電
極１２を平面的共通切断面１８でせん断し、同時に第３
図（ｃ）の如く、チップ搭載部°１１が下方にいくよう
に分離変形させる。この変形の状態は、第３図（ｂ）の
入方向から見た状態が第３図（ｃ）であるが、同しく第
３図（ｂ）のＢ方向から見た状態は、第３図（ｄ）、（
ｅ）、（ｆ）の如（チップ搭載電極部１１とリード引出
し電極１２のいずれか一方を変形させるか、双方を変形
させるかを選択し用途に応して最適化を図ることか出来
る。To obtain the above structure, as shown in FIG. 3(a), the raw material of the lead frame is punched to obtain a lead frame 31 in which the chip mounting part and the lead extraction electrode part are integrated. Next, as shown in FIG. 3(b), the chip mounting part 1] and the lead extraction electrode 12 are sheared at the planar common cutting surface 18, and at the same time the third
As shown in Figure (c), the chip mounting portion 11 is separated and deformed downward. The state of this deformation is shown in FIG. 3(c) when viewed from the entrance direction of FIG. (d), (
As shown in e) and (f), it is possible to select whether to deform either one or both of the chip mounting electrode section 11 and the lead extraction electrode 12, and to optimize the process according to the application.
このような構成を得るには、例えばプレス機械を用い
平面的に見て切断面が重なる如き切断（シェアリング）
１８とし、かつリード部を変形させればよい。To obtain such a configuration, for example, a press machine is used.
Cutting where the cut surfaces overlap when viewed from above (sharing)
18 and the lead portion may be deformed.
なお本発明は実施例のみに限らず、種々の応用か可能で
ある。例えば第３図（ａ）の一体化構造３１はケミカル
エツチングで形成することも可能である。Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, the integrated structure 31 shown in FIG. 3(a) can be formed by chemical etching.
又第３図（ｂ）の平面的共通切断面１８は、無視できる
ような細いレーザビーム等によって形成することも可能
である。また上記実施例の３端子以外に２．４，５，６
．８端子等にも適用可能である。第４図に５端子の場合
の実施例を示す。Further, the planar common cutting surface 18 shown in FIG. 3(b) can also be formed by a laser beam, etc., which is so thin that it can be ignored. In addition to the 3 terminals in the above embodiment, 2.4, 5, and 6 terminals
．． It is also applicable to 8 terminals, etc. FIG. 4 shows an embodiment in the case of five terminals.
上記構成による効果は、第１に同一のモールド体］６の
平面積でチップ搭載部１１の面積を拡大することと、第
２にはチップ１４のエツジとリードワイヤー１５との接
近によるタッチを防止することである。The effects of the above configuration are, firstly, that the area of the chip mounting portion 11 is expanded by the planar area of the same mold body]6, and secondly, that the edge of the chip 14 and the lead wire 15 are prevented from touching due to their proximity. It is to be.
まずチップ搭載部１１の面積は、第２図に示す如〈従来
技術によるチップ搭載部面積／モールド平面積２１に対
して本発明による同化２２は大幅に向上している。First, as shown in FIG. 2, the area of the chip mounting portion 11 is significantly improved by the assimilation 22 according to the present invention compared to the chip mounting portion area/mold plane area 21 according to the prior art.
第２図において、通常のモールド体の平面寸法で区分す
ると次の（Ａ）〜（Ｄ）か標準サイズとなり、
パッケージの大きさ パッケージの縦横（Ａ） ３
２１６タイプ （３，２ｍ＋ｅ Ｘ １．６ ｍ
ｍ ）（Ｂ） ２１２５タイプ （２，０ｍＩ
ＩＸ Ｌ、２５ｍｍ ）（Ｃ） ＬＧＣＩ８タイプ
（１，６ｍｍ Ｘ Ｏ，８ｍｍ ）（Ｄ） １
００５タイプ （１，０ｍｍ Ｘ ０．５ ｍｍ
）これらのグラフの各点に示される様に従来技術を比
較すると、（Ａ）では約１，３倍、（Ｂ）では約１．４
倍、（Ｃ）では約 １６倍、（Ｄ）では約 １．９倍と
なる。In Figure 2, if we classify the planar dimensions of a normal molded body, the following (A) to (D) are the standard sizes.Package size Length and width of the package (A) 3
216 type (3.2m+e x 1.6m
m ) (B) 2125 type (2,0mI
IX L, 25mm) (C) LGCI8 type
(1,6mm x O,8mm) (D) 1
005 type (1.0mm x 0.5mm
) Comparing the conventional technologies as shown at each point in these graphs, (A) is about 1.3 times more expensive, and (B) is about 1.4 times more expensive.
(C) is about 16 times, and (D) is about 1.9 times.
次にチップエツジとリードワイヤーの接近にっいては、
従来技術の場合、リードワイヤーのループコントロール
等でこれらのギャップ１３を拡大する必要かあるか、本
発明では充分にギャップ１７に余裕かあり、又リードワ
イヤー１５の所要長さも短かくすることが可能になる。Next, regarding the proximity of the tip edge and lead wire,
In the case of the conventional technology, is it necessary to enlarge these gaps 13 by loop control of the lead wire, etc.?In the present invention, the gap 17 has a sufficient margin, and the required length of the lead wire 15 can also be shortened. become.
［発明の効果］
以上説明した如く本発明によれば、チップ搭載部の面積
をより拡大でき、またチップのエツジとリードワイヤー
との接近によるタッチを防止できるため、超小型パッケ
ージ内に多大の機能をもり込むためにチップの搭載能力
を拡大できるものである。[Effects of the Invention] As explained above, according to the present invention, it is possible to further expand the area of the chip mounting portion, and it is also possible to prevent the edge of the chip and the lead wire from coming close to each other, thereby providing a large amount of functionality in an ultra-small package. It is possible to expand the chip mounting capacity to incorporate more information.
第１図（ａ）は本発明の実施例の平面図、同図（ｂ）は
同断面図、第２図は同効果を示す特性図、第３図は同実
施例の装置を得る工程図、第４図は本発明の異なる実施
例の平面図、第５図（ａ）は従来装置の平面図、同図（
ｂ）は同断面図である。
１１・・チップ搭載部、１２・・・リード引出し電極部
、１４・・・半導体チップ、１５・・・リードワイヤー
１６・・・モールド体（パッケージ）、１７・・・リー
ドワイヤーとチップのエツジとのギャップ、１８・・・
チップ搭載部とり一ト引出し電極部の共通切断面。
出願人代理人 弁理士 鈴 江 武 彦第
図
モールド体の平面積
第
図
（ＣＩ）
第
図Fig. 1(a) is a plan view of an embodiment of the present invention, Fig. 1(b) is a sectional view thereof, Fig. 2 is a characteristic diagram showing the same effect, and Fig. 3 is a process diagram for obtaining the device of the embodiment. , FIG. 4 is a plan view of a different embodiment of the present invention, FIG. 5(a) is a plan view of a conventional device, and FIG.
b) is the same sectional view. 11...Chip mounting part, 12...Lead extraction electrode part, 14...Semiconductor chip, 15...Lead wire 16...Mold body (package), 17...Lead wire and chip edge Gap, 18...
Common cutting surface of the chip mounting area and the lead-out electrode area. Applicant's representative Patent attorney Takehiko Suzue Diagram Planar area diagram of mold body (CI) Diagram
Claims (1)
見て同一切断面となり、前記チップ搭載部のチップ搭載
面とリード引出し電極面が、側面的に見て同一平面上に
なく上下にずらした事を特徴とする半導体装置。The chip mounting part and the end of the lead extraction electrode are on the same cutting plane when viewed from above, and the chip mounting surface of the chip mounting part and the lead extraction electrode surface are not on the same plane when viewed from the side but are shifted up and down. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18053590A JPH0468560A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18053590A JPH0468560A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0468560A true JPH0468560A (en) | 1992-03-04 |
Family
ID=16084967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18053590A Pending JPH0468560A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0468560A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58171839A (en) * | 1982-03-25 | 1983-10-08 | テキサス・インスツルメンツ・インコ−ポレ−テツド | Method of mounting package for semiconductor device |
| JPS60261162A (en) * | 1984-06-07 | 1985-12-24 | Toshiba Corp | Semiconductor device |
| JPH02110961A (en) * | 1988-10-19 | 1990-04-24 | Dainippon Printing Co Ltd | Semiconductor element lead frame structure and manufacture thereof |
-
1990
- 1990-07-10 JP JP18053590A patent/JPH0468560A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58171839A (en) * | 1982-03-25 | 1983-10-08 | テキサス・インスツルメンツ・インコ−ポレ−テツド | Method of mounting package for semiconductor device |
| JPS60261162A (en) * | 1984-06-07 | 1985-12-24 | Toshiba Corp | Semiconductor device |
| JPH02110961A (en) * | 1988-10-19 | 1990-04-24 | Dainippon Printing Co Ltd | Semiconductor element lead frame structure and manufacture thereof |
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