JPH0454395B2 - - Google Patents
Info
- Publication number
- JPH0454395B2 JPH0454395B2 JP5345479A JP5345479A JPH0454395B2 JP H0454395 B2 JPH0454395 B2 JP H0454395B2 JP 5345479 A JP5345479 A JP 5345479A JP 5345479 A JP5345479 A JP 5345479A JP H0454395 B2 JPH0454395 B2 JP H0454395B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor
- silicon nitride
- nitride film
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 43
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 230000005684 electric field Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 25
- 239000000758 substrate Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000003031 high energy carrier Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Thyristors (AREA)
- Formation Of Insulating Films (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】
本発明はシリコンナイトライド膜又はシリコン
酸化膜とシリコンナイトライド膜との２重層を有
するデバイスに関し、特に上記ナイトライド膜又
は２重層を介して対向する対向領域と半導体領域
の間の電流・電圧特性を制御したり、対向領域に
印加したバイアスの極性とは逆の極性の電圧又は
電流を取り出したりすることのできる半導体デバ
イスとその集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device having a double layer of a silicon nitride film or a silicon oxide film and a silicon nitride film. The present invention relates to a semiconductor device and its integrated circuit that can control the current/voltage characteristics between the two regions or extract a voltage or current with a polarity opposite to the polarity of a bias applied to an opposing region.
本発明は、第１図に示すように対向領域１０と
半導体領域１００と、この２つの領域の間にシリ
コンナイトライド膜又はシリコン酸化膜とシリコ
ンナイトライド膜との２重層１をシリコンナイト
ライド膜が半導体領域に接するように構成した構
成要素を有する半導体デバイスに対しての改良で
ある。しかるに、このような従来の半導体デバイ
スは、上記の構成要素により、第２図に示すよう
な電流制御型の負性抵抗特性（ないし導通状態と
遮断状態を持つスイツチ特性）を示すことができ
る。本発明においてもこの特長はそのままに受け
継ぐので、まず、こうした従来の半導体デバイス
に認められたと同じ構造部分に関し、説明を始め
る。 As shown in FIG. 1, the present invention includes an opposing region 10, a semiconductor region 100, and a silicon nitride film or a double layer 1 of a silicon oxide film and a silicon nitride film between these two regions. This is an improvement to a semiconductor device having a component configured such that it is in contact with a semiconductor region. However, such a conventional semiconductor device can exhibit current-controlled negative resistance characteristics (or switch characteristics having a conducting state and a cutoff state) as shown in FIG. 2 due to the above-mentioned components. Since the present invention inherits this feature as it is, we will begin by explaining the same structural parts as those found in such conventional semiconductor devices.
第１図の構成要素は対向領域としてAl蒸着膜
を用い、シリコンナイトライド膜としては約90Å
の熱窒化膜を半導体領域としてのｎ形シリコン基
板上に成長させたものである。なお、対向領域は
導電性の領域を形成するものならば他の金属膜、
半導体膜などを用いてもよい。 The components shown in Figure 1 use an Al vapor deposited film as the opposing region, and the silicon nitride film has a thickness of approximately 90 Å.
A thermal nitride film is grown on an n-type silicon substrate as a semiconductor region. Note that the opposing region may be made of other metal film, as long as it forms a conductive region.
A semiconductor film or the like may also be used.
半導体領域をシリコンのみならず、GaP、
InP、GaAs等の化合物半導体を用いることがで
きる。GaPの場合、ｎ形１Ω−cmの基板を半導体
領域として用いた場合に、“導通状態”において
表面での発光が観察された。この場合、第１図の
構成要素は発光半導体デバイスとして用いること
ができる。 The semiconductor region is not limited to silicon, but also GaP,
Compound semiconductors such as InP and GaAs can be used. In the case of GaP, when an n-type 1 Ω-cm substrate was used as a semiconductor region, light emission at the surface was observed in the "conductive state". In this case, the components of FIG. 1 can be used as light emitting semiconductor devices.
シリコンナイトライド膜は、半導体領域がシリ
コンである場合は900℃〜1200℃の温度で酸素含
有量を特に少なくした窒素又はアンモニアガス雰
囲気中で10分〜数時間加熱（熱窒化）することに
より得られる。また半導体領域がシリコン以外の
場合は600℃〜800℃でシランとアンモニアを原料
として化学蒸着法によつて得られる。この化学蒸
着法によればシリコンの場合にも適用できる。熱
窒化に際して微量の酸素の混入により、シリコン
窒化膜の上にシリコン酸化膜が成長することがあ
るが、30Å前後までは第２図と同様良好な電気特
性を示す。シリコンナイトライド膜の厚さは20Å
〜約150Åまで第２図のような特性が得られ、同
図でＢ点の電流（保持電流）はシリコンナイトラ
イド膜が薄い程大きくなり、Ｂ点の電圧はシリコ
ンナイトライド膜厚の増加と共に膜厚の厚い部分
で増加する。 If the semiconductor region is silicon, a silicon nitride film can be obtained by heating (thermal nitriding) for 10 minutes to several hours in a nitrogen or ammonia gas atmosphere with a particularly low oxygen content at a temperature of 900°C to 1200°C. It will be done. If the semiconductor region is made of a material other than silicon, it can be obtained by chemical vapor deposition using silane and ammonia as raw materials at 600° C. to 800° C. This chemical vapor deposition method can also be applied to silicon. Although a silicon oxide film may grow on the silicon nitride film due to the incorporation of a small amount of oxygen during thermal nitriding, the film exhibits good electrical characteristics up to about 30 Å as shown in FIG. 2. The thickness of silicon nitride film is 20Å
The characteristics shown in Figure 2 are obtained up to about 150 Å, and in the figure, the current at point B (holding current) increases as the silicon nitride film becomes thinner, and the voltage at point B increases as the silicon nitride film thickness increases. Increases in thicker film parts.
このような構成要素群からなる半導体デバイス
に対し、本発明に従つて更に半導体領域と整流接
合を有する第３の領域を設けるとにより、新しい
機能が賦与される。すなわち、第３図は半導体領
域１００がｎ形半導体の場合のその具体例の１つ
で、対向領域１０から注入された高エネルギーキ
ヤリアによつて発生した少数キヤリアである正孔
を、ｎ形半導体領域１００に接して少数キヤリア
である正孔の拡散又はドリフトによる到達距離以
内に設けられた第３の領域であるｐ形半導体領域
１０１Ｂで集めると、対向領域１０に負バイアス
を印加したにも拘らず領域１０１Ｂからは正電位
を取り出すことができる。要するに第４図に示す
ように特性を有し、対向領域１０に印加したバイ
アスと半導体領域に関して極性反転をした電流・
電圧を出力する電源としても用いることができ
る。これは集積回路等において極性の異なるバイ
アスを得るのに好都合である。第５図はこの応用
の具体例を示す。図に示すように高不純物濃度ｎ
形領域１００ｂ上に１０14〜１０18のオーダーの
ｎ形領域１００ａを形成した基板表面中にＰチヤ
ンネル絶縁ゲートトランジスタとｐ形ベースを持
つマルチコレクタのnpnバイポーラトランジスタ
を同時に作り込むことができるが、この２つの素
子を同一基板内で同時に動作させるためには負電
源と正電源が必要となる。ところが第３図に示し
た本発明の具体例を更に応用すれば、必要な外部
電源は一種類ですますことができる。断面図ａに
おいて、領域１１０，１１１はそれぞれ絶縁ゲー
トトランジスタのソースおよびドレイン領域を示
し、１１２は絶縁ゲートを示し、１１３はゲート
絶縁膜を示す。領域１０は対向領域、１はシリコ
ンナイトライド膜又はシリコン酸化膜とシリコン
ナイトライド膜の２重層よりなる領域、１０１Ｂ
は薄膜１を通過して来た高エネルギーキヤリアに
よつて領域１００ａ表面で発生した少数キヤリア
を収集する領域であり薄膜１と半導体領域１００
ａの接合面から少数キヤリアの到達範囲内に設け
られる。領域１０１Ｂは領域１００ａの逆導電形
の領域で、本具体例ではｐ形である。領域１０４
Ａと１０４Ｂは領域１０１Ｂ中に形成され、領域
１０１Ｂとは逆導電形の領域で、npnトランジス
タのマルチコレクタを形成する。上記npnトラン
ジスタのベースは前述のキヤリア収集領域１０１
Ｂと共通で、エミツタは基板１００ａ，１００ｂ
で形成されている。同図中、CT1と示した部分は
ｂ図の等価回路CT1に示すように対向領域１０に
負バイアスを印加して動作するnpnトランジスタ
出力の増幅回路又は論理回路となる。一方Q1と
示した部分はｂ図の等価回路に示すようなＰチヤ
ンネル絶縁ゲートトランジスタであり、負バイア
スで動作する回路素子として用いることができ
る。従つて、本発明を用いれば、従来両極性の２
つの電源が必要であつた集積回路を１つの電源で
動作させることができるようになる。なお、ｂ図
の等価回路において、各端子に示されている符号
はａ図の電極又は領域から引き出された端子であ
ることを示す。更に第５図では高エネルギー電子
によつて発生した正孔を集める領域とバイポーラ
トランジスタのベース領域とが共通であり、高密
度な集積回路が実現される。 By further providing a third region having a semiconductor region and a rectifying junction according to the present invention, a new function is imparted to a semiconductor device made of such a group of components. That is, FIG. 3 shows a specific example where the semiconductor region 100 is an n-type semiconductor. When collected in the p-type semiconductor region 101B, which is a third region provided in contact with the region 100 and within the diffusion or drift distance of holes, which are minority carriers, even though a negative bias is applied to the opposing region 10, First, a positive potential can be taken out from the region 101B. In short, it has the characteristics as shown in FIG.
It can also be used as a power source that outputs voltage. This is convenient for obtaining biases with different polarities in integrated circuits and the like. Figure 5 shows a concrete example of this application. As shown in the figure, high impurity concentration n
A P-channel insulated gate transistor and a multi-collector npn bipolar transistor having a p-type base can be simultaneously fabricated in the substrate surface in which an n-type region 100a of the order of 10 14 to 10 18 is formed on the shape region 100b. In order to operate these two elements simultaneously within the same substrate, a negative power source and a positive power source are required. However, if the specific example of the present invention shown in FIG. 3 is further applied, only one type of external power source is required. In cross-sectional view a, regions 110 and 111 respectively represent the source and drain regions of an insulated gate transistor, 112 represents an insulated gate, and 113 represents a gate insulating film. Region 10 is a facing region, 1 is a region consisting of a silicon nitride film or a double layer of a silicon oxide film and a silicon nitride film, and 101B
is a region that collects minority carriers generated on the surface of the region 100a by high-energy carriers that have passed through the thin film 1;
It is provided within the reach of the minority carrier from the joint surface of a. Region 101B is a region of the opposite conductivity type to region 100a, and is p-type in this specific example. Area 104
A and 104B are formed in the region 101B and have a conductivity type opposite to that of the region 101B, forming a multi-collector of the npn transistor. The base of the npn transistor is the carrier collection region 101 mentioned above.
In common with B, the emitters are on the substrates 100a and 100b.
It is formed of. In the figure, a portion indicated as CT 1 is an npn transistor output amplifier circuit or logic circuit that operates by applying a negative bias to the opposing region 10, as shown in the equivalent circuit CT 1 in figure b. On the other hand, the portion indicated as Q1 is a P-channel insulated gate transistor as shown in the equivalent circuit of Figure b, and can be used as a circuit element that operates with negative bias. Therefore, if the present invention is used, the conventional bipolar two
Integrated circuits that previously required two power supplies can now be operated with one power supply. In addition, in the equivalent circuit of figure b, the symbol shown on each terminal indicates that it is a terminal drawn out from the electrode or region of figure a. Further, in FIG. 5, the region for collecting holes generated by high-energy electrons and the base region of the bipolar transistor are common, and a high-density integrated circuit is realized.
第５図ａに示すようにチヤンネル領域１０５
Ａ，１０５Ｂを作れば、領域１０１Ｂは領域（１
００ａ＋１００ｂ）をソース領域１０４Ａ，１０
４Ｂをドレインとする電界効果トランジスタのゲ
ートとしても、正孔収集領域と共通に作ることが
できる。この場合は領域１０１ＢはＰ形半導体で
はなくても、整流接合を領域１００ａとの間に形
成する物質（金属又は１００ａとヘテロ接合を形
成する半導体）でもよい。この集積回路を直結形
の論理回路として動作させるためには、ゲート領
域１０１Ｂとソース領域（１００ａ＋１００ｂ）
とが０バイアスでもチヤンネル領域が空乏してい
るようなチヤネルの不純物濃度、寸法関係が選ば
れる。 Channel region 105 as shown in FIG.
A, 105B, area 101B becomes area (1
00a+100b) as source regions 104A, 10
It can also be formed as a gate of a field effect transistor having 4B as a drain, in common with the hole collecting region. In this case, the region 101B does not have to be a P-type semiconductor, but may be a material that forms a rectifying junction with the region 100a (a metal or a semiconductor that forms a heterojunction with the region 100a). In order to operate this integrated circuit as a directly connected logic circuit, a gate region 101B and a source region (100a+100b) are required.
The impurity concentration and dimension relationship of the channel is selected such that the channel region is depleted even when the bias is 0.
半導体領域と整流接合を有する第３の領域１０
１Ｂを、第６図の点線で示すように対向領域１０
下に一部重なるように設けるか、あるいは、同図
に示すように対向領域の絶縁膜２上へ延在した部
分１０ａ下へ一部重なるように設けた場合は、第
３の領域１０１Ｂを制御領域とし、対向領域１０
と半導体領域１００間のスイツチング特性のブレ
ークオーバー電圧（第２図のＡ点の電圧）又は保
持電圧（第２図のＢ点の電圧）を制御することが
できる。更に半導体領域と対向領域間電流電圧特
性を第７図のように第３の領域の電圧を変化させ
て制御することができる。 Third region 10 having a semiconductor region and a rectifying junction
1B, as shown by the dotted line in FIG.
If the third region 101B is provided so as to partially overlap below, or if it is provided so as to partially overlap below the portion 10a extending onto the insulating film 2 of the opposing region as shown in the figure, the third region 101B is controlled. area and the opposing area 10
The breakover voltage (voltage at point A in FIG. 2) or holding voltage (voltage at point B in FIG. 2) of the switching characteristic between the semiconductor region 100 and the semiconductor region 100 can be controlled. Furthermore, the current-voltage characteristics between the semiconductor region and the opposing region can be controlled by changing the voltage in the third region as shown in FIG.
このとき、第３の領域１０１Ｂと対向領域間の
入力特性は負性抵抗特性がみられた。 At this time, a negative resistance characteristic was observed as the input characteristic between the third region 101B and the opposing region.
上記の説明において、半導体領域の導電形を逆
とし、正孔と電子とを逆にした場合も本発明は成
立することは言うまでもない。上記説明では半導
体領域１００は基板であつたが、他の半導体基板
表面に分離された状態で設けられてもよいし、絶
縁基板上の半導体層でもよい。電界効果トランジ
スタのソース又はドレインあるいはバイポーラト
ランジスタのコレクタと半導体領域とを共通領域
とすれば、トランジスタを番地選択用素子とする
高密度スタテイツク形メモリ集積回路を実現する
ことができる。 In the above description, it goes without saying that the present invention also works when the conductivity type of the semiconductor region is reversed and the holes and electrons are reversed. In the above description, the semiconductor region 100 is a substrate, but it may be provided separately on the surface of another semiconductor substrate, or it may be a semiconductor layer on an insulating substrate. If the source or drain of a field effect transistor or the collector of a bipolar transistor and a semiconductor region are used as a common region, a high-density static type memory integrated circuit using the transistor as an address selection element can be realized.
第１図は本発明の構成要素断面図、第２図は第
１図構成要素の特性図、第３図〜第７図は本発明
の実施例を示す。
図中、１はシリコンナイトライド又はシリコン
酸化膜とシリコンナイトライドの２重層からなる
薄膜、１０は対向領域、１００は半導体領域、１
０１Ｂは第３の領域を示す。
FIG. 1 is a sectional view of the components of the present invention, FIG. 2 is a characteristic diagram of the components of FIG. 1, and FIGS. 3 to 7 show embodiments of the present invention. In the figure, 1 is silicon nitride or a thin film consisting of a double layer of silicon oxide film and silicon nitride, 10 is an opposing region, 100 is a semiconductor region, 1
01B indicates the third area.
Claims (1)
領域と、前記半導体領域と対向領域間に設けられ
たシリコンナイトライド膜又はシリコン酸化膜と
シリコンナイトライド膜との２重層とから少なく
ともなる半導体デバイスにおいて、前記半導体領
域と接し、整流性接合を有する第３の領域を設
け、該第３の領域から前記半導体領域に関して前
記対向領域に印加するバイアスとは逆極性の電流
又は電圧を発生するか、又は前記第３の領域を制
御領域として前記半導体領域と対向領域間の電
流・電圧特性を制御することを特徴とする半導体
デバイス。 ２ 半導体領域と、該半導体領域に対向する対向
領域と、前記半導体領域と対向領域間に設けられ
たシリコンナイトライド膜又はシリコン酸化膜と
シリコンナイトライド膜との２重層と、前記半導
体領域に接して形成された逆導電型の第３の領域
と、該第３の領域と整流性の接合を形成するよう
に設けられた第４の領域とからなり、前記第４の
領域をドレインとする電界効果トランジスタ又は
前記第４の領域をコレクタとするバイポーラトラ
ンジスタを集積した構造を含むことを特徴とする
集積回路。[Claims] 1. A semiconductor region, a counter region facing the semiconductor region, and a silicon nitride film or a double layer of a silicon oxide film and a silicon nitride film provided between the semiconductor region and the counter region. A semiconductor device comprising at least a third region in contact with the semiconductor region and having a rectifying junction, and a current or voltage having a polarity opposite to a bias applied from the third region to the opposing region with respect to the semiconductor region. A semiconductor device characterized in that the third region is used as a control region to control current/voltage characteristics between the semiconductor region and an opposing region. 2. A semiconductor region, a counter region facing the semiconductor region, a silicon nitride film or a double layer of a silicon oxide film and a silicon nitride film provided between the semiconductor region and the counter region, and a double layer of a silicon oxide film and a silicon nitride film in contact with the semiconductor region. a third region of the opposite conductivity type formed by a third region, and a fourth region provided to form a rectifying junction with the third region, and an electric field with the fourth region as a drain. An integrated circuit comprising a structure in which effect transistors or bipolar transistors having the fourth region as a collector are integrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5345479A JPS55146959A (en) | 1979-05-02 | 1979-05-02 | Semiconductor device having silicon nitride film and integrated circuit using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5345479A JPS55146959A (en) | 1979-05-02 | 1979-05-02 | Semiconductor device having silicon nitride film and integrated circuit using the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63217955A Division JPH01117369A (en) | 1988-08-31 | 1988-08-31 | Semiconductor device provided with silicon nitride film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55146959A JPS55146959A (en) | 1980-11-15 |
| JPH0454395B2 true JPH0454395B2 (en) | 1992-08-31 |
Family
ID=12943297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5345479A Granted JPS55146959A (en) | 1979-05-02 | 1979-05-02 | Semiconductor device having silicon nitride film and integrated circuit using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55146959A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58168275A (en) * | 1982-03-29 | 1983-10-04 | Fujitsu Ltd | Semiconductor device |
| JPH01117369A (en) * | 1988-08-31 | 1989-05-10 | Agency Of Ind Science & Technol | Semiconductor device provided with silicon nitride film |
| US5312684A (en) * | 1991-05-02 | 1994-05-17 | Dow Corning Corporation | Threshold switching device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49131391A (en) * | 1973-04-19 | 1974-12-17 | ||
| JPS5115396A (en) * | 1974-07-30 | 1976-02-06 | Hochiki Co | KEIHOSHISUTEMU |
| JPS5234678A (en) * | 1975-06-18 | 1977-03-16 | Sperry Rand Corp | Multiiterminal inversion controlled semiconductor device |
| JPS54156486A (en) * | 1978-05-31 | 1979-12-10 | Toshiba Corp | Negative resistance element |
-
1979
- 1979-05-02 JP JP5345479A patent/JPS55146959A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49131391A (en) * | 1973-04-19 | 1974-12-17 | ||
| JPS5115396A (en) * | 1974-07-30 | 1976-02-06 | Hochiki Co | KEIHOSHISUTEMU |
| JPS5234678A (en) * | 1975-06-18 | 1977-03-16 | Sperry Rand Corp | Multiiterminal inversion controlled semiconductor device |
| JPS54156486A (en) * | 1978-05-31 | 1979-12-10 | Toshiba Corp | Negative resistance element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55146959A (en) | 1980-11-15 |
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