JPH04290244A - Aging method of semiconductor device - Google Patents
Aging method of semiconductor deviceInfo
- Publication number
- JPH04290244A JPH04290244A JP3054315A JP5431591A JPH04290244A JP H04290244 A JPH04290244 A JP H04290244A JP 3054315 A JP3054315 A JP 3054315A JP 5431591 A JP5431591 A JP 5431591A JP H04290244 A JPH04290244 A JP H04290244A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- socket
- aging
- electrodes
- pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000032683 aging Effects 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims description 24
- 230000002431 foraging effect Effects 0.000 claims description 7
- 238000003825 pressing Methods 0.000 claims description 7
- 239000011295 pitch Substances 0.000 description 12
- 230000002950 deficient Effects 0.000 description 9
- 229920002379 silicone rubber Polymers 0.000 description 7
- 239000004945 silicone rubber Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 238000007689 inspection Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はチップ状態の半導体をエ
−ジングする方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for aging semiconductors in chip form.
【０００２】0002
【従来の技術】ＬＳＩ等の半導体装置は、通常、その製
造工程において、パッケ−ジング後、即ち、組立て後に
エ−ジングと呼ばれる加速寿命試験が行われる。2. Description of the Related Art Semiconductor devices such as LSIs are normally subjected to an accelerated life test called aging during the manufacturing process after packaging, that is, after assembly.
【０００３】ここで予め代表的な従来の製造工程につい
て触れておくと、先ず、前工程と呼ばれる工程において
、所定の回路機能が作り込まれたＬＳＩチップを多数含
むウェハが完成し、プロ−ブ検査でウェハ内のＬＳＩチ
ップは一個一個所定の回路機能が正常に動作するか否か
を検査される。その後、後工程と呼ばれる工程に入り、
先ずダイシング工程でウェハ内のＬＳＩチップは一個一
個分離され、プロ−ブ検査で良品とされたＬＳＩチップ
はパッケ−ジングされる。パッケ−ジング工程では、Ｌ
ＳＩチップはリ−ドピンとともに樹脂で封止されたり、
セラミックスの容器に気密封止され、完成品としての形
状を整える。また、テ−プ上に形成されたリ−ド端子に
ＬＳＩチップの電極を接続したＴＡＢ（Ｔａｐｅ Ａｕ
ｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）として完成品となる
。[0003] Here, let us first mention a typical conventional manufacturing process. First, in a process called the pre-process, a wafer containing a large number of LSI chips with predetermined circuit functions is completed, and then a probe is placed on the wafer. During the inspection, each LSI chip within the wafer is inspected to determine whether or not predetermined circuit functions operate normally. After that, we enter a process called the post-process.
First, the LSI chips within the wafer are separated one by one in a dicing process, and those LSI chips that are found to be good by probe inspection are packaged. In the packaging process, L
The SI chip is sealed with resin along with the lead pins,
It is hermetically sealed in a ceramic container and shaped into a finished product. In addition, TAB (Tape Au
The finished product is bonded (bonded).
【０００４】次に前述のような完成品としての形状を整
えたＬＳＩは、エ−ジング工程に入る。エ−ジングとは
、個々の半導体装置に所定の電圧を印加して所定の雰囲
気温度、例えば、１２５℃で所定時間、例えば、４〜９
６時間動作させる加速寿命試験である。その目的は、周
知のように、半導体装置の回路動作を安定化させるとと
もに、寿命の短い半導体装置を不良品として顕在化させ
ることにある。具体的な方法は、通常、エ−ジングに必
要な配線、部品を施したエ−ジングボ−ド上のソケット
にＬＳＩを収納し、高温恒温槽の中で電気的動作を行う
。この工程で、プロ−ブ検査で良品とされたＬＳＩであ
っても、温度ストレス、電気的ストレスを所定時間加え
られることによってある割合で不良となる。このような
ＬＳＩは前工程でなんらかの不良要因が作り込まれたに
もかかわらず、プロ−ブ検査では不良とはならず、エ−
ジング工程で不良現象が顕在化する。エ−ジング工程で
発生した不良品は次の選別工程で除去され、良品のみが
出荷される。従って適切な条件でエ−ジングを行うこと
により、実使用に十分な耐用年数をもった製品のみを出
荷できるようになり、エ−ジングは半導体装置の製造工
程で必要不可欠な工程となっている。Next, the LSI that has been shaped into a finished product as described above undergoes an aging process. Aging refers to applying a predetermined voltage to each semiconductor device at a predetermined ambient temperature, e.g. 125°C, for a predetermined time, e.g.
This is an accelerated life test in which the device is operated for 6 hours. As is well known, the purpose is to stabilize the circuit operation of the semiconductor device and to make semiconductor devices with a short lifespan appear as defective products. Specifically, the LSI is usually housed in a socket on an aging board provided with the wiring and parts necessary for aging, and the LSI is electrically operated in a high-temperature constant temperature bath. In this process, even if the LSI is found to be good in the probe test, a certain percentage of the LSI becomes defective due to the application of temperature stress and electrical stress for a predetermined period of time. Although such LSIs have some kind of defective factor built into them in the previous process, they are not found to be defective in probe inspection and are
Defect phenomena become apparent during the ging process. Defective products generated in the aging process are removed in the next sorting process, and only good products are shipped. Therefore, by aging under appropriate conditions, it becomes possible to ship only products that have a sufficient service life for actual use, and aging has become an essential process in the manufacturing process of semiconductor devices. .
【０００５】このエ−ジングはスクリ−ニングもしくは
バ−ンインと呼ばれることもあり、１９８０年、１月１
５日、株式会社工業調査会発行、日本マイクロエレクト
ロニクス協会編「ＩＣ化実装技術」２５９ペ−ジに説明
されている。[0005] This aging is sometimes called screening or burn-in, and was introduced on January 1, 1980.
This is explained in ``IC Mounting Technology'', published by Kogyo Kenkyukai Co., Ltd. on the 5th, edited by the Japan Microelectronics Association, page 259.
【０００６】[0006]
【発明が解決しようとする課題】しかし、従来のエ−ジ
ング工程には以下に述べるような問題がある。However, the conventional aging process has the following problems.
【０００７】先ず、従来技術におけるエ−ジング工程は
、先に述べたようにパッケ−ジングの後に実施されるた
め、寿命の短い不良チップをも組み立ててしまい、結果
的に無駄な作業を行ったことになる。First, as mentioned above, the aging process in the conventional technology is carried out after packaging, which results in the assembly of defective chips with short lifespans, resulting in wasted work. It turns out.
【０００８】さらに、エ−ジング後の選別工程で大量の
不良品が検出された場合、その殆どの原因はウェハ完成
までの前工程にあることが多く、その不良情報を早く前
工程にフィ−ドバックすべきであるにもかかわらず、パ
ッケ−ジング後にエ−ジングを行うために、不良情報の
フィ−ドバックが遅れてしまうという問題がある。Furthermore, when a large number of defective products are detected in the sorting process after aging, most of the causes are likely to be found in the previous process until wafer completion. Even though feedback should be provided, there is a problem in that feedback of defective information is delayed because aging is performed after packaging.
【０００９】更に、近年、高密度実装技術が急速に発達
しつつある中で、半導体装置をチップ状態で実装したい
という要求が高まっているが、チップ状態ではエ−ジン
グが実施されておらず、信頼性的に不安が残るという問
題がある。Furthermore, with the rapid development of high-density packaging technology in recent years, there has been an increasing demand for semiconductor devices to be mounted in chip form, but aging is not performed in chip form. There is a problem of reliability concerns.
【００１０】本発明の目的は、半導体装置をパッケ−ジ
ングする前のチップ状態でエ−ジングする方法を提供す
ることにある。An object of the present invention is to provide a method for aging a semiconductor device in a chip state before packaging.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
、本発明は前記チップを収納するソケット底部及び前記
ソケットが搭載されるエ−ジングボ−ドに、前記チップ
を真空吸引するパイプを通すための貫通孔を設け、前記
チップを前記ソケットの所定の位置に載置するとともに
、前記貫通孔を通した前記パイプにより仮固定した後、
前記ソケットの押圧蓋により完全固定し、前記エ−ジン
グボ−ドに電源及び信号電圧を供給して前記チップを動
作させ、チップの状態で複数個を一括してエ−ジングす
るようにした。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for passing a pipe for vacuum suction of the chip through the bottom of the socket for storing the chip and the aging board on which the socket is mounted. After providing a through hole and placing the chip in a predetermined position of the socket and temporarily fixing it with the pipe passed through the through hole,
The chips were completely fixed by the pressing lid of the socket, and power and signal voltage were supplied to the aging board to operate the chips, thereby aging a plurality of chips at once in the state of chips.
【００１２】また、前記ソケット内の底部に、前記貫通
孔を設けた弾性体シ−トを搭載し、その上に前記チップ
の電極に対応させて配置した給電用電極と前記給電用電
極よりも粗いピッチで配列されて前記給電用電極のそれ
ぞれに接続された拡大ピッチ電極と前記貫通孔を設けた
フレキシブル基板を載置し、前記チップの電極を前記給
電用電極に対向させて位置決めし、前記貫通孔を通した
前記パイプにより前記チップを仮固定した後、前記ソケ
ットの押圧蓋により完全固定し、前記エ−ジングボ−ド
に電源及び信号電圧を供給して前記チップを動作させ、
チップの状態で複数個を一括してエ−ジングするように
した。[0012] Further, an elastic sheet provided with the through-hole is mounted on the bottom of the socket, and a power supply electrode disposed on the elastic sheet corresponding to the electrode of the chip, and a power supply electrode larger than the power supply electrode. A flexible substrate provided with enlarged pitch electrodes arranged at a coarse pitch and connected to each of the power supply electrodes and the through hole is mounted, and the electrodes of the chip are positioned to face the power supply electrodes, and the After temporarily fixing the chip with the pipe passed through the through hole, completely fixing it with the pressing lid of the socket, supplying power and signal voltage to the aging board to operate the chip,
It is now possible to age multiple pieces at once while they are still in chip form.
【００１３】[0013]
【作用】前記チップを収納するソケット底部及び前記ソ
ケットが搭載されるエ−ジングボ−ドに設けた貫通孔は
、前記チップを真空吸引するパイプを通すための役割を
果たす。前記パイプは、前記チップを前記ソケットの所
定の位置に載置した後、前記チップを真空吸引して所定
の位置に仮固定する。前記ソケットの押圧蓋は、前記チ
ップを前記ソケットの所定の位置に完全固定する。[Operation] The through holes provided in the bottom of the socket for storing the chip and in the aging board on which the socket is mounted serve to pass a pipe for vacuum suctioning the chip. After the chip is placed in a predetermined position of the socket, the pipe temporarily fixes the chip in a predetermined position by vacuum suction. A press-on lid of the socket completely secures the chip in place in the socket.
【００１４】また、上記チップの電極は、フレキシブル
基板の給電用電極に接触して導通する。この給電用電極
は拡大ピッチ電極に導通されている。前記拡大ピッチ電
極は、ソケットの内部接続端子に対向、当接して導通す
る。この当接導通部分は、そのピッチが拡大されている
ので容易に確実に対向、当接して導通される。前記各当
接部はソケットと押圧蓋との間に、弾性体シ−トを介し
て挾圧されて当接圧力が与えられて確実に導通する。前
記フレキシブル基板及び弾性体シ−トに設けた貫通孔は
、前記チップを真空吸引するパイプを通すための役割を
果たす。[0014] Furthermore, the electrodes of the chip contact the power supply electrodes of the flexible substrate and are electrically conductive. This power feeding electrode is electrically connected to the enlarged pitch electrode. The enlarged pitch electrodes face and abut the internal connection terminals of the socket and are electrically conductive. Since the pitch of the abutting conductive portions is enlarged, the conductive portions easily and reliably face each other and abut against each other for conduction. Each of the abutting portions is clamped between the socket and the pressing lid via an elastic sheet to apply contact pressure to ensure electrical continuity. The through holes provided in the flexible substrate and the elastic sheet serve to pass a pipe for vacuum suctioning the chip.
【００１５】[0015]
【実施例】図１は本発明に係るエ−ジング方法の一実施
例を示す分解斜視図、図２は同じく断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an exploded perspective view showing an embodiment of the aging method according to the present invention, and FIG. 2 is a sectional view thereof.
【００１６】本図はエ−ジングボ−ド６上に一個のソケ
ット１のみ示してあるが、本発明を実施する場合は複数
のソケット１が搭載されることが望ましい。Although this figure shows only one socket 1 on the aging board 6, it is desirable that a plurality of sockets 1 be mounted when carrying out the present invention.
【００１７】この実施例に用いる主な装置は、底部に貫
通孔１９をもつソケット１、貫通孔２１をもつシリコン
ゴムシ−ト２、貫通孔３５をもつフレキシブル基板３、
位置合わせ用ハ−フミラ−４、チップ５、エ−ジングボ
−ド６及びパイプ７から構成されている。The main devices used in this embodiment are a socket 1 having a through hole 19 at the bottom, a silicone rubber sheet 2 having a through hole 21, a flexible substrate 3 having a through hole 35,
It consists of a half mirror 4 for alignment, a chip 5, an aging board 6, and a pipe 7.
【００１８】ソケット１は耐熱性プラスチック又はセラ
ミック製であり、通常のＬＳＩソケットと同様の構造（
即ち、チップ状態ではなく、パッケ−ジ済のＬＳＩのエ
−ジングを行うためのソケットに類似した構成）であっ
て、外部リ−ド１１と、外部リ−ド１１に導通され、か
つ弾性の内部接続端子１２とを備えている。そして、こ
のソケット１の底部には、チップ５が位置する中央部に
パイプ７を通すための貫通孔１９を設けてある。The socket 1 is made of heat-resistant plastic or ceramic, and has the same structure as a normal LSI socket (
In other words, it is not in a chip state, but has a structure similar to a socket for aging a packaged LSI. An internal connection terminal 12 is provided. A through hole 19 is provided at the bottom of the socket 1 to allow the pipe 7 to pass through the central portion where the chip 5 is located.
【００１９】また、ソケット１の内部底面には、シリコ
ンゴム製の弾性体シ−ト（シリコンゴムシ−トと略する
）２を収納するための凹部１３を設け、この凹部１３の
底面にシリコンゴムシ−ト２を接着してある。そしてシ
リコンゴムシ−ト２の中央部にパイプ７を通すための貫
通孔２１を設けてある。Further, a recess 13 is provided on the inner bottom surface of the socket 1 for storing an elastic sheet 2 made of silicone rubber (abbreviated as silicone rubber sheet). A rubber sheet 2 is attached. A through hole 21 for passing the pipe 7 is provided in the center of the silicone rubber sheet 2.
【００２０】フレキシブル基板３は、チップ状態の半導
体装置であるチップ５と、パッケ−ジされた半導体装置
に適合するソケット１の内部接続端子１２とを電気的に
接続するための部材であり、中央部にパイプ７を通すた
めの貫通孔３５を設けてある。本例のフレキシブル基板
３は、ポリイミド材で構成してあり、その上面にはチッ
プ５のチップ電極に当接する多数の給電用電極３２が配
置され、その下面には、多数の給電用電極３２のそれぞ
れに導通された拡大ピッチ電極３１が配列されている。
３３は、給電用電極３２と拡大ピッチ電極３１とを接続
している銅箔パタ−ンである。The flexible substrate 3 is a member for electrically connecting the chip 5, which is a semiconductor device in the form of a chip, and the internal connection terminal 12 of the socket 1, which is compatible with a packaged semiconductor device. A through hole 35 for passing the pipe 7 is provided in the portion. The flexible substrate 3 of this example is made of a polyimide material, and a large number of power feeding electrodes 32 that contact the chip electrodes of the chip 5 are arranged on its upper surface, and a large number of power feeding electrodes 32 are arranged on its lower surface. Enlarged pitch electrodes 31 are arranged, each of which is electrically connected. 33 is a copper foil pattern connecting the power feeding electrode 32 and the enlarged pitch electrode 31.
【００２１】フレキシブル基板３とソケット１とを相互
に位置決めするため、ソケット１には二個の位置決めピ
ン１４を設けてあり、一方、フレキシブル基板３には二
個のガイド孔３４を設けてある。１７は、押圧蓋１５が
位置決めピン１４と干渉しないように設けた逃がし穴で
ある。In order to position the flexible substrate 3 and the socket 1 with respect to each other, the socket 1 is provided with two positioning pins 14, and the flexible substrate 3 is provided with two guide holes 34. Reference numeral 17 denotes an escape hole provided so that the pressing lid 15 does not interfere with the positioning pin 14.
【００２２】フレキシブル基板３は、本例では厚さ２５
ミクロンのポリイミドフィルムで構成し、適度の可撓性
と耐熱性とを得た。またフレキシブル基板３の下面に設
けた拡大ピッチ電極３１は、本例では厚さ１８ミクロン
の銅箔によって構成し、内部接続端子１２に対応させて
配列し、金メッキを施して導通の確実性を図った。また
、フレキシブル基板３の上面に設けた給電用電極３２は
、チップ５のチップ電極に対応して配列し、金メッキを
施してフレキシブル基板面から２０ミクロン突出させ、
突起状電極とした。これによりチップ電極と給電用電極
３２との接触、導通が確実となる。しかし、チップ電極
が突起状であれば、給電用電極３２は必ずしも突起状に
形成する必要はない。給電用電極３２と拡大ピッチ電極
３１とは、フレキシブル基板３に設けたスル−ホ−ルを
介して、銅箔パタ−ン３３によって接続する。The flexible substrate 3 has a thickness of 25 mm in this example.
It is made of micron polyimide film and has appropriate flexibility and heat resistance. In addition, the enlarged pitch electrodes 31 provided on the lower surface of the flexible substrate 3 are made of copper foil with a thickness of 18 microns in this example, arranged to correspond to the internal connection terminals 12, and plated with gold to ensure continuity. Ta. Further, the power supply electrodes 32 provided on the upper surface of the flexible substrate 3 are arranged corresponding to the chip electrodes of the chip 5, and are plated with gold to protrude by 20 microns from the surface of the flexible substrate.
It was made into a protruding electrode. This ensures contact and continuity between the chip electrode and the power supply electrode 32. However, if the chip electrode has a protruding shape, the power feeding electrode 32 does not necessarily need to be formed in a protruding shape. The power feeding electrode 32 and the enlarged pitch electrode 31 are connected by a copper foil pattern 33 through a through hole provided in the flexible substrate 3.
【００２３】押圧蓋１５の下面には、チップ５の上面に
当接する凹部１６が設けられている。また、図２に示し
たように押圧蓋１５を閉じた状態に保持しうるように、
図１に示すロック機構１８が設けられている。A recess 16 is provided on the lower surface of the pressing lid 15 and comes into contact with the upper surface of the chip 5. Further, as shown in FIG. 2, so that the press lid 15 can be held in a closed state,
A locking mechanism 18 shown in FIG. 1 is provided.
【００２４】本発明方法を適用してエ−ジングを行うに
は、シリコンゴムシ−ト２が載置されたソケット１にフ
レキシブル基板３を設置し、チップ５を真空吸着するた
めのパイプ７をエ−ジングボ−ド６の下方より、貫通孔
６１、１９、２１及び３５を通してフレキシブル基板３
のわずか上方にまで挿入する。次に、チップ５のチップ
電極とフレキシブル基板３の給電用電極３２とを対向さ
せるようにしてチップ５をフレキシブル基板３の上方に
配置し、両者の間にハ−フミラ−４を挿入して光学装置
（図示せず）によりチップ５とフレキシブル基板３との
位置合わせを行う。次に、ハ−フミラ−４を退避させて
チップ５をフレキシブル基板３に接触させるとともに、
パイプ７によりチップ５を真空吸着して、パイプ７を下
方に引っ張るような所定の力を加えてチップ５を仮固定
する。その後、押圧蓋１５を閉じ（図２の状態）、ロッ
ク機構１８によりチップ５をソケット１に完全固定して
、パイプ７を貫通孔６１、１９、２１及び３５から引き
抜く。この状態でシリコンゴムシ−ト２の弾性とフレキ
シブル基板３の可撓性とによって、チップ電極５１が給
電用電極３２に接触し、銅箔パタ−ン３３、内部接続端
子１２を介して外部リ−ド１１に導通される。To carry out aging using the method of the present invention, the flexible substrate 3 is installed in the socket 1 on which the silicone rubber sheet 2 is placed, and the pipe 7 for vacuum suctioning the chip 5 is connected. The flexible substrate 3 is inserted through the through holes 61, 19, 21 and 35 from below the aging board 6.
Insert it slightly above. Next, the chip 5 is placed above the flexible substrate 3 so that the chip electrode of the chip 5 and the power supply electrode 32 of the flexible substrate 3 are opposed to each other, and the half mirror 4 is inserted between the two to provide optical power. The chip 5 and the flexible substrate 3 are aligned using a device (not shown). Next, the half mirror 4 is retracted to bring the chip 5 into contact with the flexible substrate 3, and
The chip 5 is vacuum-adsorbed by the pipe 7, and a predetermined force such as pulling the pipe 7 downward is applied to temporarily fix the chip 5. Thereafter, the press lid 15 is closed (the state shown in FIG. 2), the chip 5 is completely fixed in the socket 1 by the locking mechanism 18, and the pipe 7 is pulled out from the through holes 61, 19, 21, and 35. In this state, the chip electrode 51 comes into contact with the power supply electrode 32 due to the elasticity of the silicone rubber sheet 2 and the flexibility of the flexible substrate 3, and an external lead is connected via the copper foil pattern 33 and the internal connection terminal 12. - is electrically connected to the lead 11.
【００２５】これによりエ−ジングボ−ド６に搭載した
複数のソケット１に同様の操作を行ってチップ５を収納
し、外部リ−ド１１に電源及び信号電圧を印加してチッ
プ５を作動させ、所定温度で所定時間のエ−ジングを行
う。[0025] As a result, the chip 5 is housed by performing the same operation on the plurality of sockets 1 mounted on the aging board 6, and the chip 5 is activated by applying power and signal voltage to the external lead 11. , aging is performed at a predetermined temperature for a predetermined time.
【００２６】なお、チップ５とフレキシブル基板３との
位置合わせは、ハ−フミラ−４を用いるものに限定する
ものではなく、他の光学的手段を用いても良い。Note that the alignment between the chip 5 and the flexible substrate 3 is not limited to the use of the half mirror 4, and other optical means may be used.
【００２７】このように本実施例の場合の効果について
、その要点を略述すると次のようである。The main points of the effects of this embodiment can be summarized as follows.
【００２８】先ず、チップを真空吸着するパイプを用い
てソケット内の所定の位置にチップを仮固定した後、押
圧蓋により完全固定するようにしたため、確実にソケッ
ト内の給電用電極とチップの電極とを接触させることが
できる。First, the chip was temporarily fixed in a predetermined position in the socket using a vacuum suction pipe, and then completely fixed with a pressure lid, so that the power supply electrode in the socket and the electrode of the chip were securely connected. can be brought into contact with.
【００２９】また、拡大ピッチ電極をもつフレキシブル
基板を用いるので、パッケ−ジングされたＬＳＩに用い
る内部接続端子ピッチの粗いソケットにチップを収納で
きるようになった。更に、半導体装置の品種を変更して
、チップの形状やチップ電極の個数、形状が変わった場
合も、各仕様に適応するフレキシブル基板を用いること
で同一のソケットを使用することができる。Furthermore, since a flexible substrate with enlarged pitch electrodes is used, chips can be accommodated in sockets with coarse internal connection terminal pitches used in packaged LSIs. Furthermore, even if the type of semiconductor device is changed and the shape of the chip and the number and shape of the chip electrodes are changed, the same socket can be used by using a flexible substrate that adapts to each specification.
【００３０】[0030]
【発明の効果】本発明によれば、半導体装置をパッケ−
ジングする前のチップ状態でエ−ジングすることが出来
るので、エ−ジングによってチェックアウトされる不良
品にパッケ−ジングを施す無駄が省かれる。[Effects of the Invention] According to the present invention, a semiconductor device can be packaged.
Since the chip state before aging can be aged, there is no need to package defective products that are checked out by aging.
【図１】本発明の半導体装置のエ−ジング方法の一実施
例を示す分解斜視図。FIG. 1 is an exploded perspective view showing an embodiment of the aging method for a semiconductor device of the present invention.
【図２】本発明の半導体装置のエ−ジング方法の一実施
例を示す断面図。FIG. 2 is a cross-sectional view showing an embodiment of the method for aging a semiconductor device of the present invention.
１…ソケット、 ２…シリコンゴムシ−ト、 ３…フレキシブル基板、 ４…位置合わせ用ハ−フミラ−、 ５…チップ、 ６…エ−ジングボ−ド、 ７…パイプ、 １１…外部リ−ド、 １２…内部接続端子、 １４…位置決めピン、 １５…押圧蓋、 １６…凹部、 １８…ロック機構、 ３１…拡大ピッチ電極、 ３２…給電用電極、 ３３…銅箔パタ−ン、 ３４…ガイド孔、 １９、２１、３５、６１…貫通孔。 1...Socket, 2...Silicone rubber sheet, 3...Flexible board, 4...Half mirror for positioning, 5... Chip, 6...Aging board, 7...Pipe, 11...External lead, 12...Internal connection terminal, 14...Positioning pin, 15...pressing lid, 16... recess, 18...Lock mechanism, 31...Enlarged pitch electrode, 32...Power feeding electrode, 33...Copper foil pattern, 34...Guide hole, 19, 21, 35, 61...through holes.
Claims (2)
方法において、前記チップを収納するソケット底部及び
前記ソケットが搭載されるエ−ジングボ−ドに、前記チ
ップを真空吸引するパイプを通すための貫通孔を設け、
前記チップを前記ソケットの所定の位置に載置するとと
もに、前記貫通孔を通した前記パイプにより仮固定した
後、前記ソケットの押圧蓋により完全固定し、前記エ−
ジングボ−ドに電源及び信号電圧を供給して前記チップ
を動作させ、前記チップの状態に応じて複数個を一括し
てエ−ジングするようにしたことを特徴とする半導体装
置のエ−ジング方法。1. A method of aging a semiconductor device in a chip state, wherein a pipe for vacuum suctioning the chip is passed through the bottom of a socket for storing the chip and an aging board on which the socket is mounted. Provide a through hole,
The chip is placed in a predetermined position in the socket and temporarily fixed by the pipe passed through the through hole, and then completely fixed by the pressing lid of the socket.
A method for aging a semiconductor device, characterized in that a power supply and a signal voltage are supplied to a aging board to operate the chips, and a plurality of chips are aged at once according to the condition of the chips. .
に、前記貫通孔を設けた弾性体シ−トを搭載し、その上
に前記チップの電極に対応して配置した給電用電極と前
記給電用電極よりも粗いピッチで配列されて前記給電用
電極のそれぞれに接続された拡大ピッチ電極と前記貫通
孔を設けたフレキシブル基板を載置し、前記チップの電
極を前記給電用電極に対向させて位置決めした、半導体
装置のエ−ジング方法。2. According to claim 1, an elastic sheet provided with the through hole is mounted on the bottom of the socket, and a power feeding electrode arranged on the elastic sheet corresponding to the electrode of the chip and the A flexible substrate provided with enlarged pitch electrodes arranged at a pitch coarser than the power supply electrodes and connected to each of the power supply electrodes and the through hole is mounted, and the electrodes of the chip are opposed to the power supply electrodes. A method for aging semiconductor devices that are positioned using
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3054315A JP2917553B2 (en) | 1991-03-19 | 1991-03-19 | Aging method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3054315A JP2917553B2 (en) | 1991-03-19 | 1991-03-19 | Aging method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04290244A true JPH04290244A (en) | 1992-10-14 |
| JP2917553B2 JP2917553B2 (en) | 1999-07-12 |
Family
ID=12967153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3054315A Expired - Lifetime JP2917553B2 (en) | 1991-03-19 | 1991-03-19 | Aging method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2917553B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945834A (en) * | 1993-12-16 | 1999-08-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
-
1991
- 1991-03-19 JP JP3054315A patent/JP2917553B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945834A (en) * | 1993-12-16 | 1999-08-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
| US6005401A (en) * | 1993-12-16 | 1999-12-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
| US6323663B1 (en) | 1993-12-16 | 2001-11-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2917553B2 (en) | 1999-07-12 |
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