JPH04243196A - Manufacture of ceramic multilayer wiring board - Google Patents
Manufacture of ceramic multilayer wiring boardInfo
- Publication number
- JPH04243196A JPH04243196A JP417091A JP417091A JPH04243196A JP H04243196 A JPH04243196 A JP H04243196A JP 417091 A JP417091 A JP 417091A JP 417091 A JP417091 A JP 417091A JP H04243196 A JPH04243196 A JP H04243196A
- Authority
- JP
- Japan
- Prior art keywords
- laminate
- conductive pin
- wiring board
- multilayer wiring
- green sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000005429 filling process Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はセラミック多層配線基板
の製造方法、特にグリーンシート法により製造されるセ
ラミック多層配線基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ceramic multilayer wiring board, and more particularly to a method of manufacturing a ceramic multilayer wiring board manufactured by a green sheet method.
【０００２】0002
【産業上の利用分野】従来のセラミック基板の製造方法
は、特開昭６２−１３４９９７号に示されるように、ア
ルミナ、ガラス等の粉体と溶剤とをして泥漿とし、この
泥漿をスリップキャスティング法にて成膜しグリーンシ
ートとし、これを所定の形状に切断する。そして、パン
チングにてグリーンシートの上下間を接続するためのス
ルーホールを形成し、このスルーホールに印刷法により
導体パターンペースト及びビアフィルペーストを埋め込
み、更に、このグリーンシートを所定数積層し、加圧・
加温して圧着した後、脱バインダー及び焼成を実施して
製造していた。[Industrial Application Field] The conventional method for manufacturing ceramic substrates is as shown in JP-A-62-134997, in which powders of alumina, glass, etc. and a solvent are made into a slurry, and this slurry is slip cast. A green sheet is formed by the method, and this is cut into a predetermined shape. Then, a through hole is formed by punching to connect the upper and lower sides of the green sheet, and a conductive pattern paste and via fill paste are embedded in this through hole by a printing method.Furthermore, a predetermined number of these green sheets are stacked and processed. Pressure/
After heating and press-bonding, the binder was removed and the product was fired.
【０００３】0003
【発明が解決しようとする課題】上述した従来のセラミ
ック多層配線基板の製造方法は、スルーホールー形成・
ビアフィル工程を行なっているため、
１．スルーホール形成もれ
２．積層前に導体ペースト抜けによるアビオープン３．
導体ペーストが柱の役割をしてしまうため、スルーホー
ルビアが湾曲し、グリーンシート自体に圧力がかからず
、収縮率がばらつくなどの欠点がある。[Problems to be Solved by the Invention] The above-mentioned conventional method for manufacturing a ceramic multilayer wiring board involves forming through-holes and
Due to the via fill process, 1. Through hole formation leakage 2. 3. Open due to conductor paste missing before lamination.
Since the conductive paste acts as a pillar, the through-hole vias are curved, no pressure is applied to the green sheet itself, and the shrinkage rate varies.
【０００４】0004
【課題を解決するための手段】本発明は、回路パターン
が形成されたグリーンシートを複数枚積層し、これを熱
圧着して積層体を形成する第１の工程と、前記積層体を
加熱すると共に加熱した導体ピンを挿入し、所定の前記
回路パターン間を導通させる第２の工程とを含んで構成
されている。[Means for Solving the Problems] The present invention includes a first step of laminating a plurality of green sheets each having a circuit pattern formed thereon and bonding them together by thermocompression to form a laminate, and heating the laminate. The method also includes a second step of inserting a heated conductor pin to establish electrical continuity between the predetermined circuit patterns.
【０００５】[0005]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.
【０００６】図１は本発明は一実施例を示す断面図であ
る。FIG. 1 is a sectional view showing one embodiment of the present invention.
【０００７】図２は本実施例のグリーンシートの積層を
例を示す斜視図である。図１および図２において、グリ
ーンシート１は導体配線２を施されたシートであり、こ
のグリーンシート１を複数枚積層し、熱プレス機により
熱圧着し積層体３を形成する。このとき、スルーホール
形成工程がないためスルーホール形成もれがない。また
、ビアフィル工程がないためグリーンシート１自体にか
かる圧力の安定化が図れる。そして、導体ピン４を積層
体に挿入する。このとき、導体ピンは予め高温に加熱さ
れており、積層体も同様に加熱しているため、容易にピ
ンを挿入することができる。FIG. 2 is a perspective view showing an example of stacking of green sheets according to this embodiment. In FIGS. 1 and 2, a green sheet 1 is a sheet provided with conductor wiring 2, and a plurality of green sheets 1 are laminated and bonded under heat using a hot press machine to form a laminate 3. At this time, since there is no through-hole forming step, there is no omission of through-hole formation. Further, since there is no via fill process, the pressure applied to the green sheet 1 itself can be stabilized. Then, the conductor pin 4 is inserted into the laminate. At this time, since the conductor pins have been previously heated to a high temperature and the laminate is also heated in the same way, the pins can be easily inserted.
【０００８】以上の工程の後、上下にはみ出した余分な
導体ピン４を切断し、更に、この積層体３を脱バインダ
ー及び焼成を行う。[0008] After the above steps, the excess conductor pins 4 protruding upward and downward are cut off, and the laminate 3 is further debindered and fired.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、積層・熱
圧着後に導体ピンを挿入することによってスルーホール
形成・ビアフィルを行なう必要がなくなる。そのため、
スルーホールの形成もれ、ビア抜け・ビアオープン、ビ
アペーストの湾曲によりプレス圧がグリーンシートにか
からないため収縮率のばらつき等の問題点をなくする効
果がある。As described above, the present invention eliminates the need for through-hole formation and via filling by inserting conductor pins after lamination and thermocompression bonding. Therefore,
This has the effect of eliminating problems such as through-hole formation failure, via omission/opening, and bending of the via paste, since pressing pressure is not applied to the green sheet, such as variations in shrinkage rate.
【図１】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】本実施例のグリーンシートの積層の例を示す斜
視図である。FIG. 2 is a perspective view showing an example of stacking green sheets according to this embodiment.
１ グリーンシート ２ 導体配線 ３ 積層体 ４ 導体ピン 1 Green sheet 2 Conductor wiring 3 Laminated body 4 Conductor pin
Claims (1)
ートを複数枚積層し、これを熱圧着して積層体を形成す
る第１の工程と、前記積層体を加熱すると共に加熱した
導体ピンを挿入し、所定の前記回路パターン間を導通さ
せる第２の工程とからなるセラミック多層配線基板の製
造方法。1. A first step of laminating a plurality of green sheets on which a circuit pattern is formed and thermocompression bonding them to form a laminate, and heating the laminate and inserting a heated conductor pin. . A method for manufacturing a ceramic multilayer wiring board, comprising: a second step of providing electrical continuity between the predetermined circuit patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP417091A JP2861406B2 (en) | 1991-01-18 | 1991-01-18 | Manufacturing method of ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP417091A JP2861406B2 (en) | 1991-01-18 | 1991-01-18 | Manufacturing method of ceramic multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04243196A true JPH04243196A (en) | 1992-08-31 |
| JP2861406B2 JP2861406B2 (en) | 1999-02-24 |
Family
ID=11577263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP417091A Expired - Lifetime JP2861406B2 (en) | 1991-01-18 | 1991-01-18 | Manufacturing method of ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2861406B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002204044A (en) * | 2000-10-23 | 2002-07-19 | Ibiden Co Ltd | Interlayer connecting structure and its manufacturing method |
-
1991
- 1991-01-18 JP JP417091A patent/JP2861406B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002204044A (en) * | 2000-10-23 | 2002-07-19 | Ibiden Co Ltd | Interlayer connecting structure and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2861406B2 (en) | 1999-02-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19981110 |