JPH04177734A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04177734A JPH04177734A JP30569990A JP30569990A JPH04177734A JP H04177734 A JPH04177734 A JP H04177734A JP 30569990 A JP30569990 A JP 30569990A JP 30569990 A JP30569990 A JP 30569990A JP H04177734 A JPH04177734 A JP H04177734A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electric field
- region
- base
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 14
- 108091006146 Channels Proteins 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業−にの利用分野］
本発明は、ＰＮ接合に逆バイアス電圧を印加したとき、
安定な素子特性を有する高耐圧プレーナ形半導体装置に
関するものである、。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides that when a reverse bias voltage is applied to a PN junction,
The present invention relates to a high voltage planar semiconductor device having stable device characteristics.
［従来の技術］
従来の゛１′、導体装置を、プレーナ形高耐圧Ｎ Ｉ）
Ｎ１〜ランジスタを例にとり説明すれは、第２図に示す
ように、Ｎ“高濃度ＩｎにＮ Ｊｆ’ｉを成まくさせ
たＮ型゛１′、導体基板１の−Ｌ表面２の選択された箇
所に、例えば選択拡散技術により、ＰＮ接合形成領域と
しての１〕型のベース領域３か、その表面を１ミ表面２
に露出させて形成されている。このベース領域３により
、半導体基板１との間でＰＮ接合領域５が設けられ、こ
のベース領域；３内には、その表面を−１：、表面２に
露出させて、例えば選択拡散技術により形成されたＮ型
エミッタ領域４が設けられている。なお、ベース領域３
及びエミｙり領域４に（ま、それぞれ電極Ｂ、Ｔ＝：が
、１健けら才している（−１−、ｉ己のように形成され
たＰＮ接合領域５の周囲であって、このＰ Ｎ接合に逆
バイアスを印加したとき空乏Ｊ：’Ｊが広がり１：↑る
範囲を包囲するように、エミッタ領域４と同時に拡散さ
れたＮ型のチャネルス１−ツバ６が形成され、電極Ｓが
設けられている。。[Prior art] The conventional 1' conductor device was replaced with a planar type high withstand voltage N I)
Taking N1~ transistor as an example, as shown in FIG. For example, by selective diffusion technology, the base region 3 of type 1 as a PN junction formation region or its surface is made into a 1 mm surface 2.
It is formed by being exposed to A PN junction region 5 is provided between the base region 3 and the semiconductor substrate 1, and a PN junction region 5 is formed in the base region 3 by, for example, a selective diffusion technique, with its surface exposed to the surface 2. An N-type emitter region 4 is provided. Note that base area 3
and in the emitter region 4 (respectively, the electrodes B and T=: are around the PN junction region 5 formed like (-1-, i), and this When a reverse bias is applied to the P-N junction, the depletion J:'J expands and N-type channels 1-flange 6 are formed at the same time as the emitter region 4 so as to surround the range 1:↑, and the electrode S is provided.
而して、］二２主表面２には、Ｓｉｎ、から成る絶縁膜
としての酸化膜７が生成されている。な才９、Ｃば基板
１の他の］ミ表面８にオーミック接触したコレクタ電極
である。Thus, on the main surface 2, an oxide film 7 made of Sin and serving as an insulating film is formed. 9, C is a collector electrode in ohmic contact with the other surface 8 of the substrate 1.
［発明が解決しようとする課題］
従来の半導体装置は以１−のような構造になっているの
で、ＰＮ接合に逆バイアス電圧を印加した場合、空乏層
の広がり得る範囲は、ベース電極Ｂの外周とチャネルス
トッパ電極Ｓの外周とに跨がる領域Ｘの距離で決定され
る。このため、この距離を、半導体装置の有する耐圧特
性に合わせて決定するのが通常であった。然るに、従来
の半導体装置は、耐圧特性以１−の逆バイアス電圧を無
理に印加した場合、前記領域Ｘに高電界が発生し、その
結果、前記領域Ｘの−・部で電界集中が起こり、ベース
電極Ｂとチャネルストッパ電極Ｓとの間でマイクロプラ
ズマが発生してしまう。[Problem to be Solved by the Invention] Since the conventional semiconductor device has the structure as shown in 1- below, when a reverse bias voltage is applied to the PN junction, the range in which the depletion layer can expand is within the range of the base electrode B. It is determined by the distance of the region X spanning the outer periphery and the outer periphery of the channel stopper electrode S. For this reason, this distance has usually been determined in accordance with the breakdown voltage characteristics of the semiconductor device. However, in conventional semiconductor devices, when a reverse bias voltage of 1- below the breakdown voltage characteristic is forcibly applied, a high electric field is generated in the region X, and as a result, electric field concentration occurs in the region X. Microplasma is generated between the base electrode B and the channel stopper electrode S.
この耐圧特性以Ｉ−の逆バイアス電圧を長期にわたり印
加し、マイクロプラズマを長期間発生させると、ＰＮ接
合の接合破壊を起こし、結果的に半導体装置の破壊に至
るという問題点があ一部た１゜本発明はかかる問題点を
ｆＮ′消すへくなされたもので高面・１圧、高信頼性を
し１った甲、４休装置を提供することを「ｊ的とする。If a reverse bias voltage higher than this withstand voltage characteristic is applied for a long period of time and microplasma is generated for a long period of time, there is a problem that the PN junction will be destroyed and the semiconductor device will be destroyed as a result. 1. It is an object of the present invention to provide a high-surface, single-pressure, high-reliability device that has been designed to eliminate such problems.
［課題を解決するための「１段］
本発明に係わる゛ｌ’導体装ｊｉ１ｊは、ＩＩＮ接合形
成領域（ベース領域３）の表面に設けた電極Ｂの外周と
環状領域（チャネルス１〜ツバ６）に設けた電極Ｓの外
周とに跨がる部分に形成された絶縁１漠（酸化膜７）−
１−に、Ｉ” Ｎ接合形成領域（ベース領域；３）を囲
む少なくとも１個の環状電極Ｋを設けたものである。[One step to solve the problem] The conductor device according to the present invention has a structure that connects the outer periphery of the electrode B provided on the surface of the IIN junction formation region (base region 3) and the annular region (channels 1 to flange). 6) Insulation 1 (oxide film 7) formed on the part spanning the outer periphery of the electrode S provided in
1- is provided with at least one annular electrode K surrounding an I''N junction forming region (base region; 3).
［作用］
本発明における半導体装置は、少なくとも１個の環状電
極Ｋが絶縁膜としての酸化膜７１−に設けられ、電界を
分散させる。[Function] In the semiconductor device according to the present invention, at least one annular electrode K is provided on the oxide film 71- as an insulating film to disperse an electric field.
［実施例］
以下、図面に示す実施例に基づき本発明の詳細な説明す
る。第１図は本発明に係わる半導体装置を示す断面図で
、同図において第２図と同一の部材については同一の符
号を（−Ｊ’ Ｌ、詳細な説明は省略する。同図におい
て、絶縁膜としての酸化膜７上にはＰＮ接合形成領域と
してのベース領域３をとり囲む環状電極Ｋが施されてい
る。[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings. FIG. 1 is a cross-sectional view showing a semiconductor device according to the present invention. In the same figure, the same members as in FIG. A ring-shaped electrode K surrounding the base region 3 as a PN junction formation region is provided on the oxide film 7 as a film.
次に動作について説明する１゜
本発明に係オ）る半導体装置に逆バイアス電圧を印加し
た場合、ベース電極Ｂとチャネルストッパ電極Ｓとの間
には、印加電圧とベース電極Ｂ・チャネルストッパ電極
Ｓ間の距離、すなわち前述の領域Ｘの距離とで決定され
る電界が発生する。然るに、この電界は、設計的にかん
がみ無理に高くした高電圧を印加したりすると一点で電
界集中し、前記領域Ｘの一部でマイクロプラズマを発生
するが、本発明においては環状電極Ｋがベース電極Ｂと
チャネルストッパ電極Ｓとの間に位置するため、前記の
電界を分散させるように働く。そのため、−点での電界
集中を防ぎ、マイクロプラズマの発生を無くすことがで
きる５゜
なお、上記実施例では、環状電極Ｋを１つだけ設けてい
るが、環状電極にの設置数はいくらでもよく、設置数を
多くした方が電界の分散により犬きな効果を奏する。Next, when a reverse bias voltage is applied to the semiconductor device according to 1. (e) of the present invention, the operation will be explained. An electric field is generated that is determined by the distance between the regions S, that is, the distance of the region X described above. However, if this electric field is applied with a high voltage that is too high considering the design, the electric field will concentrate at one point and generate microplasma in a part of the region X. However, in the present invention, the annular electrode K is the base. Since it is located between the electrode B and the channel stopper electrode S, it acts to disperse the electric field. Therefore, it is possible to prevent electric field concentration at the - point and eliminate the generation of microplasma.In addition, in the above embodiment, only one annular electrode K is provided, but any number of annular electrodes may be provided. , the more installed there is, the more effective the electric field will be dispersed.
また、環状電極にの［１１は設置数に応じて変えてよい
。Further, [11] on the annular electrode may be changed depending on the number of installed electrodes.
［発明の効果］
以」二のようにこの発明によれは絶縁膜にに、ｒ〕Ｎ接
合形成領域を囲む少なくとも１個の環状電極／
を設けたので電界集中を防市でき、高耐圧、高信頼性を
図った半導体装置が１）られる効果がある１゜[Effects of the Invention] As described in 2 below, this invention provides an insulating film with at least one annular electrode surrounding the N junction formation region, which prevents electric field concentration and provides high withstand voltage. 1゜ which has the effect of making semiconductor devices with high reliability 1)
第１図は本発明に係わる半導体装置を示す断面図、第２
図は従来の１１′、導体装置を示す断面図である。
図において、１は半導体基板、；３はベース領域、４は
エミッタ領域、５はＰ Ｎ接合領域、にはチャネルス１
〜ツバ、７は酸化膜、Ｂはベース電極、Ｃはコレクタ電
極、Ｅはエミッタ電極、Ｋは環状電極、Ｓはチャネルス
トッパ電極である。。
なお、図中、同一符号は同一・、または相当部分−〇−FIG. 1 is a sectional view showing a semiconductor device according to the present invention, and FIG.
The figure is a sectional view showing a conventional conductor device 11'. In the figure, 1 is a semiconductor substrate; 3 is a base region; 4 is an emitter region; 5 is a PN junction region;
- brim, 7 is an oxide film, B is a base electrode, C is a collector electrode, E is an emitter electrode, K is an annular electrode, and S is a channel stopper electrode. . In addition, in the figures, the same symbols indicate the same or corresponding parts -〇-
Claims (1)
の主表面に露出するように上記半導体基板に形成されか
つ半導体基板とは反対の導電型から成るＰＮ接合形成領
域と、上記ＰＮ接合形成領域の周囲に位置しかつ上記半
導体基板と同一でかつ上記半導体基板より高濃度の不純
物をもつ導電型から成る環状領域と、上記ＰＮ接合形成
領域の表面に設けた電極の外周と上記環状領域に設けた
電極の外周とに跨がる部分に形成された絶縁膜とから成
る半導体装置において、上記絶縁膜上に、上記ＰＮ接合
形成領域を囲む少なくとも１個の環状電極を設けたこと
を特徴とする半導体装置。a semiconductor substrate of one conductivity type; a PN junction formation region formed on the semiconductor substrate so as to be exposed on the main surface of the semiconductor substrate and of a conductivity type opposite to that of the semiconductor substrate; an annular region located in the periphery and consisting of a conductivity type that is the same as the semiconductor substrate and has a higher concentration of impurities than the semiconductor substrate; a semiconductor device comprising an insulating film formed on a portion spanning the outer periphery of the electrode, characterized in that at least one annular electrode surrounding the PN junction formation region is provided on the insulating film. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30569990A JPH04177734A (en) | 1990-11-09 | 1990-11-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30569990A JPH04177734A (en) | 1990-11-09 | 1990-11-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04177734A true JPH04177734A (en) | 1992-06-24 |
Family
ID=17948300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30569990A Pending JPH04177734A (en) | 1990-11-09 | 1990-11-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04177734A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11288949A (en) * | 1998-02-24 | 1999-10-19 | Samsung Electronics Co Ltd | Power semiconductor device using semi-insulating polysilicon (sipos) and its manufacture |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58147060A (en) * | 1982-02-08 | 1983-09-01 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Semiconductor device reducing surface electric field intensity |
| JPS62291966A (en) * | 1986-06-11 | 1987-12-18 | Nec Corp | Semiconductor device |
-
1990
- 1990-11-09 JP JP30569990A patent/JPH04177734A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58147060A (en) * | 1982-02-08 | 1983-09-01 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Semiconductor device reducing surface electric field intensity |
| JPS62291966A (en) * | 1986-06-11 | 1987-12-18 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11288949A (en) * | 1998-02-24 | 1999-10-19 | Samsung Electronics Co Ltd | Power semiconductor device using semi-insulating polysilicon (sipos) and its manufacture |
| JP4607266B2 (en) * | 1998-02-24 | 2011-01-05 | フェアチャイルドコリア半導體株式会社 | Power semiconductor device using semi-insulating polysilicon (SIPOS) and manufacturing method thereof |
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