JPH03276737A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03276737A
JPH03276737A JP2077443A JP7744390A JPH03276737A JP H03276737 A JPH03276737 A JP H03276737A JP 2077443 A JP2077443 A JP 2077443A JP 7744390 A JP7744390 A JP 7744390A JP H03276737 A JPH03276737 A JP H03276737A
Authority
JP
Japan
Prior art keywords
lead
leads
semiconductor chip
insulating tape
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2077443A
Other languages
Japanese (ja)
Inventor
Masahiko Sakurai
櫻井　正彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2077443A priority Critical patent/JPH03276737A/en
Publication of JPH03276737A publication Critical patent/JPH03276737A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve mounting efficiency and to make it possible to cope with high-density mounting by forming leads on both surface of an insulating tape. CONSTITUTION:Copper foils are bonded and laminated on both surfaces of an insulating tape 11. Leads 2a and 2b are formed by etching, tin plating and the like. Two lines of protruding electrodes 3a and 3b are arranged so that they are connected between the leads 2a and 2b on a semiconductor chip 4. The lead 2a which is formed on the surface side of the semiconductor chip 4 and the protruding electrode 3a are directly bonded by thermal contact bonding as in a conventional device. The lead 2b on the opposite surface and the protruding electrode 3b are bonded with a wire 6 comprising gold (Au) or copper (Cu) by wire bonding. Potting or transfer molding is performed, and the device is sealed with a sealing body 5.

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は半導体装置に係わり、特に高密度表面実装に好
適なものに関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to one suitable for high-density surface mounting.

（従来の技術） 近年、高密度実装化の要求が高まるなかで、Ｔ　Ａ　Ｂ
　（Ｔａｐｅ　Ａｕｔｏｍａｉｅｄ　Ｂｏｎｄｉｎｇ）
フィルムが広く用いられるに至っている。(Conventional technology) In recent years, as the demand for high-density packaging has increased, T A B
(Tape Automated Bonding)
Films have come into widespread use.

このＴＡＢフィルムを用いた従来の半導体装置の断面構
造を、第３図に示す。ポリイミド等の高耐熱性を有する
絶縁テープ１１の片面に、銅（Ｃｕ）等から成る金属箔
が接着積層された後、所定の形状にエツチング成形され
て、リード２が形成されている。搭載する半導体チップ
４には、金（Ａｕ）あるいは銅（Ｃｕ）から成る突起電
極３が形成されている。絶縁テープ１１に形成された開
孔部６に、この半導体チップ４が設置され、突起電極３
とリード２とが熱圧着法等により接合されている。そし
てエポキシ樹脂等を用いて、ポツティング成形あるいは
トランスファモールド成形等により成形された封止体５
によって封止されている。A cross-sectional structure of a conventional semiconductor device using this TAB film is shown in FIG. A metal foil made of copper (Cu) or the like is adhesively laminated on one side of an insulating tape 11 having high heat resistance such as polyimide, and then etched into a predetermined shape to form the lead 2. A protruding electrode 3 made of gold (Au) or copper (Cu) is formed on the semiconductor chip 4 to be mounted. This semiconductor chip 4 is installed in the opening 6 formed in the insulating tape 11, and the protruding electrode 3
and the lead 2 are joined by thermocompression bonding or the like. Then, the sealing body 5 is molded by potting molding, transfer molding, etc. using epoxy resin or the like.
is sealed by.

（発明が解決しようとする課題） しかし、このような従来の半導体装置は、絶縁テープ１
１の片面にのみリード２が形成されているため、実装を
平面的にしか行えず、実装面積において非効率的である
という問題があった。(Problem to be Solved by the Invention) However, such conventional semiconductor devices are
Since the lead 2 is formed only on one side of the semiconductor device 1, the mounting can only be carried out in a two-dimensional manner, resulting in a problem that the mounting area is inefficient.

本発明は上記事情に鑑みてなされたもので、実装効率を
向上させ、高密度実装化への要求に対応することができ
る半導体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that can improve packaging efficiency and meet demands for high-density packaging.

〔発明の構成〕[Structure of the invention]

（課題を解決するための手段） 本発明の半導体装置は、絶縁性テープと、絶縁性テープ
の表面に形成されたリードと、リードにそれぞれ電気的
に接続されるための突起電極を有した半導体チップと、
突起電極がリードに電気的に接続された半導体チップを
封止する封止体とを備えた装置であって、リードが絶縁
性テープの両面に形成されていることを特徴としている
。(Means for Solving the Problems) A semiconductor device of the present invention includes an insulating tape, a lead formed on the surface of the insulating tape, and a protruding electrode for electrically connecting to the lead. chips and
This device includes a sealing body for sealing a semiconductor chip in which protruding electrodes are electrically connected to leads, and is characterized in that the leads are formed on both sides of an insulating tape.

ここでリードが、絶縁性テープの半導体チップ搭載側の
表面に形成された第］のリードと、半導体チップ搭載側
と反対側の表面に形成された第２のリードとから成り、
第１のリードは突起電極に圧着接合されており、第２の
リードは突起電極にワイヤで接合されているものであっ
てもよい。Here, the lead consists of a first lead formed on the surface of the insulating tape on the semiconductor chip mounting side, and a second lead formed on the surface opposite to the semiconductor chip mounting side,
The first lead may be crimped and bonded to the protruding electrode, and the second lead may be bonded to the protruding electrode with a wire.

（作　用） 絶縁性テープの両面にリードが形成されていることによ
り、片側の面にのみ形成されている場合と比較し、同一
の面積で二倍の外部電極を設けることが可能となり、実
装密度が大幅に向上する。(Function) By forming leads on both sides of the insulating tape, it is possible to provide twice as many external electrodes in the same area compared to when leads are formed only on one side, making it easier to implement. Density is greatly improved.

ここで、半導体チップ搭載側の第１のリードが突起電極
に直接圧着接合され、反対側の第２のリードがワイヤを
介して突起電極に接合されている場合には、半導体チッ
プとリードとの間で接続に必要な面積が最小限で足り、
実装密度が向上する。Here, if the first lead on the side where the semiconductor chip is mounted is directly crimped and bonded to the protruding electrode, and the second lead on the opposite side is bonded to the protruding electrode via a wire, the connection between the semiconductor chip and the lead is The area required for connection between the two is minimal,
Improves packaging density.

（実施例） 以下、本発明の一実施例について、図面を参照して説明
する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第１図に本実施例による半導体装置の構造を示し、さら
に第２図にその縦断面構造を示す。従来の装置と異なる
のは、絶縁テープ１１の両面に銅箔が接着積層され、エ
ツチング、すず鍍金等によって、リード２ａ及び２ｂが
形成されている点である。これに対応するため、半導体
チップ４には各リード２ａ及び２ｂとの間で接続できる
ように、二列の突起電極３ａ及び３ｂが配置されている
。FIG. 1 shows the structure of a semiconductor device according to this embodiment, and FIG. 2 shows its longitudinal cross-sectional structure. The difference from conventional devices is that copper foil is adhesively laminated on both sides of an insulating tape 11, and leads 2a and 2b are formed by etching, tin plating, or the like. To cope with this, two rows of protruding electrodes 3a and 3b are arranged on the semiconductor chip 4 so as to be able to connect with each lead 2a and 2b.

リードのうち、半導体チップ４側の面に形成されている
リード２ａと突起電極３ａとの間の接続は、従来の装置
と同様に、熱圧着等により直接接合（Ｉｎｎｅｒ　Ｌｅ
ａｄ　Ｂｏｎｄｉｎｇ）されている。そして、反対面の
り一ド２ｂと突起電極３ｂとは、ワイヤボンディングに
より、金（Ａｕ）あるいは銅（Ｃｕ）等から成るワイヤ
６で接合されている。Among the leads, the connection between the lead 2a formed on the surface on the side of the semiconductor chip 4 and the protruding electrode 3a is made by direct bonding (inner Le
ad bonding). The glue 2b on the opposite side and the protruding electrode 3b are bonded by wire bonding using a wire 6 made of gold (Au), copper (Cu), or the like.

しかる後に、従来の装置と同様にポツティングあるいは
トランスファモールド成形が行われて、封止体５で封止
されている。Thereafter, potting or transfer molding is performed in the same manner as in conventional devices, and the device is sealed with a sealing body 5.

このように本実施例によれば、絶縁テープの両面にリー
ドが形成されているため、外部電極が従来と比較し、同
一の実装面積で約二倍の高密度で実装することが可能で
ある。In this way, according to this embodiment, since the leads are formed on both sides of the insulating tape, the external electrodes can be mounted at about twice the density in the same mounting area compared to the conventional method. .

上述した実施例は一例であって、本発明を限定するもの
ではない。例えば、本実施例では第１図に示されたよう
に、絶縁テープ１の両面に形成すべきリード２ａ及び２
ｂが、絶縁テープ１をはさんで対向するように配置され
ているが、ピッチをずらして配置されていてもよい。The embodiments described above are merely examples and do not limit the present invention. For example, in this embodiment, as shown in FIG.
b are arranged so as to face each other with the insulating tape 1 in between, but they may be arranged with a shifted pitch.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の半導体装置によれば、絶縁
性テープの両面にリードが形成されているため、片面に
のみ形成されている場合と比較して、同一の面積で二倍
の外部電極を設けることができ、実装密度の大幅な向上
が達成される。As explained above, according to the semiconductor device of the present invention, since the leads are formed on both sides of the insulating tape, the number of external electrodes is twice as large in the same area compared to a case where the leads are formed only on one side. can be provided, and a significant improvement in packaging density can be achieved.

半導体チップとリードとの接続が、半導体チップ搭載側
の第１のリードは突起電極に直接圧着接合されており、
反対側の第２のリードはワイヤを介して突起電極に接合
されている場合には、接続に必要な面積を最小限にする
ことができ、実装密度の向上がもたらされる。The connection between the semiconductor chip and the leads is such that the first lead on the side where the semiconductor chip is mounted is directly crimped and bonded to the protruding electrode.
When the second lead on the opposite side is connected to the protruding electrode via a wire, the area required for connection can be minimized, resulting in an improvement in packaging density.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例による半導体装置の構造を示
す平面図、第２図は同装置の縦断面構造を示す縦断面図
、第３図は従来の半導体装置の縦断面構造を示す縦断面
図である。 １・・・絶縁テープ、２ａ、２ｂ−リード、３ａ。 ３ｂ・・・突起電極、４・・・半導体チップ、５・・・
封止体、６・・・開孔部。FIG. 1 is a plan view showing the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view showing the vertical cross-sectional structure of the same device, and FIG. 3 is a vertical cross-sectional view showing the vertical cross-sectional structure of a conventional semiconductor device. FIG. 1... Insulating tape, 2a, 2b-lead, 3a. 3b... Projection electrode, 4... Semiconductor chip, 5...
Sealing body, 6...opening part.

Claims (1)

【特許請求の範囲】 １、絶縁性テープと、 前記絶縁性テープの表面に形成されたリードと、前記リ
ードにそれぞれ電気的に接続されるための突起電極を有
した半導体チップと、 前記突起電極が前記リードに電気的に接続された前記半
導体チップを封止する封止体とを備えた半導体装置にお
いて、 前記リードは前記絶縁性テープの両面に形成されている
ことを特徴とする半導体装置。 ２、前記リードは、前記絶縁性テープの前記半導体チッ
プ搭載側の表面に形成された第１のリードと、前記半導
体チップ搭載側と反対側の表面に形成された第２のリー
ドから成り、 前記第１のリードは前記突起電極に圧着接合されており
、前記第２のリードは前記突起電極にワイヤで接合され
ていることを特徴とする請求項１記載の半導体装置。[Claims] 1. An insulating tape, leads formed on the surface of the insulating tape, a semiconductor chip having protruding electrodes to be electrically connected to the leads, and the protruding electrodes. and a sealing body for sealing the semiconductor chip electrically connected to the leads, wherein the leads are formed on both sides of the insulating tape. 2. The lead includes a first lead formed on the surface of the insulating tape on the semiconductor chip mounting side and a second lead formed on the surface opposite to the semiconductor chip mounting side, and 2. The semiconductor device according to claim 1, wherein the first lead is pressure-bonded to the protruding electrode, and the second lead is bonded to the protruding electrode with a wire.
JP2077443A 1990-03-27 1990-03-27 Semiconductor device Pending JPH03276737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2077443A JPH03276737A (en) 1990-03-27 1990-03-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2077443A JPH03276737A (en) 1990-03-27 1990-03-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03276737A true JPH03276737A (en) 1991-12-06

Family

ID=13634166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2077443A Pending JPH03276737A (en) 1990-03-27 1990-03-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03276737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081093A (en) * 2005-09-14 2007-03-29 Matsushita Electric Ind Co Ltd Semiconductor device
US7569917B2 (en) 2006-06-07 2009-08-04 Oki Semiconductor Co., Ltd. Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081093A (en) * 2005-09-14 2007-03-29 Matsushita Electric Ind Co Ltd Semiconductor device
US7569917B2 (en) 2006-06-07 2009-08-04 Oki Semiconductor Co., Ltd. Semiconductor device

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