JPH03102747U - - Google Patents

Info

Publication number
JPH03102747U
JPH03102747U JP1990011553U JP1155390U JPH03102747U JP H03102747 U JPH03102747 U JP H03102747U JP 1990011553 U JP1990011553 U JP 1990011553U JP 1155390 U JP1155390 U JP 1155390U JP H03102747 U JPH03102747 U JP H03102747U
Authority
JP
Japan
Prior art keywords
grounding
signal transmission
wiring
layer substrate
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990011553U
Other languages
English (en)
Other versions
JP2502994Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990011553U priority Critical patent/JP2502994Y2/ja
Publication of JPH03102747U publication Critical patent/JPH03102747U/ja
Application granted granted Critical
Publication of JP2502994Y2 publication Critical patent/JP2502994Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す半導体集積回路
用容器の平面図、第２図は第１図のＡ−Ａ線断面
図、第３図は従来の半導体集積回路容器の上面図
、第４図は本考案の第２の実施例を示す半導体集
積回路用容器の部分平面図、第５図は本考案の第
３の実施例を示す半導体集積回路用容器の部分平
面図、第６図は第５図のＢ−Ｂ線断面図である。 ２１……第１層基板、２２……第２層基板、２
３，６１，７１……接地用金属層、３０……Ｇａ
Ａｓの半導体チツプ、３１……信号用パツド、３
２，３３……接地用パツド、３４……電源用パツ
ド、４０……ボンデイングワイヤ、５０……信号
伝送用配線、５１，５２，６０……接地用配線、
５３……電源用配線、５４，７２……スルーホー
ル、５５……リードフレーム、７０……枠状のア
ルミナ基板。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) (a) 基板上に形成される複数の信号伝送用
    配線と、 (b) 該信号伝送用配線とワイヤボンデイング
    により接続される半導体チツプの信号用パツドと
    、 (c) 前記信号伝送用配線の間に形成される接
    地用配線と、 (d) 該接地用配線とワイヤボンデイングによ
    り接続されると共に、前記信号用パツド間に形成
    される前記半導体チツプの接地用パツドと、 (e) 前記接地用配線を一括して接地する接地
    用金属層を具備することを特徴とする半導体集積
    回路用容器。 (2) (a) 第１層基板と、 (b) 該第１層基板上に形成される接地用金属
    層と、 (c) 該接地用金属層上に形成される第２層基
    板と、 (d) 該第２層基板上に形成される複数の信号
    伝送用配線と、 (e) 該信号伝送用配線とワイヤボンデイング
    により接続される半導体チツプの信号用パツドと
    、 (f) 前記信号伝送用配線の間に形成される接
    地用配線と、 (g) 該接地用配線とワイヤボンデイングによ
    り接続されると共に、前記信号用パツド間に形成
    される前記半導体チツプの接地用パツドと、 (h) 前記接地用配線と、前記第１層基板と前
    記第２層基板間に形成される接地用金属層とを電
    気的に接続するスルーホールとを具備することを
    特徴とする半導体集積回路用容器。
JP1990011553U 1990-02-09 1990-02-09 半導体集積回路装置 Expired - Lifetime JP2502994Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990011553U JP2502994Y2 (ja) 1990-02-09 1990-02-09 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990011553U JP2502994Y2 (ja) 1990-02-09 1990-02-09 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPH03102747U true JPH03102747U (ja) 1991-10-25
JP2502994Y2 JP2502994Y2 (ja) 1996-06-26

Family

ID=31515076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990011553U Expired - Lifetime JP2502994Y2 (ja) 1990-02-09 1990-02-09 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JP2502994Y2 (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693350A (en) * 1979-12-26 1981-07-28 Mitsubishi Electric Corp Armor of semiconductor device
JPS6037753A (ja) * 1983-08-10 1985-02-27 Nec Corp 半導体装置用パツケ−ジ
JPS63188963A (ja) * 1987-01-31 1988-08-04 Sumitomo Electric Ind Ltd 半導体素子搭載用パツケ−ジ
JPH01191433A (ja) * 1988-01-26 1989-08-01 Fujitsu Ltd 集積回路素子

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693350A (en) * 1979-12-26 1981-07-28 Mitsubishi Electric Corp Armor of semiconductor device
JPS6037753A (ja) * 1983-08-10 1985-02-27 Nec Corp 半導体装置用パツケ−ジ
JPS63188963A (ja) * 1987-01-31 1988-08-04 Sumitomo Electric Ind Ltd 半導体素子搭載用パツケ−ジ
JPH01191433A (ja) * 1988-01-26 1989-08-01 Fujitsu Ltd 集積回路素子

Also Published As

Publication number Publication date
JP2502994Y2 (ja) 1996-06-26

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term