JPH03102747U - - Google Patents
Info
- Publication number
- JPH03102747U JPH03102747U JP1990011553U JP1155390U JPH03102747U JP H03102747 U JPH03102747 U JP H03102747U JP 1990011553 U JP1990011553 U JP 1990011553U JP 1155390 U JP1155390 U JP 1155390U JP H03102747 U JPH03102747 U JP H03102747U
- Authority
- JP
- Japan
- Prior art keywords
- grounding
- signal transmission
- wiring
- layer substrate
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 230000008054 signal transmission Effects 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の実施例を示す半導体集積回路
用容器の平面図、第2図は第1図のA−A線断面
図、第3図は従来の半導体集積回路容器の上面図
、第4図は本考案の第2の実施例を示す半導体集
積回路用容器の部分平面図、第5図は本考案の第
3の実施例を示す半導体集積回路用容器の部分平
面図、第6図は第5図のB−B線断面図である。 21……第1層基板、22……第2層基板、2
3,61,71……接地用金属層、30……Ga
Asの半導体チツプ、31……信号用パツド、3
2,33……接地用パツド、34……電源用パツ
ド、40……ボンデイングワイヤ、50……信号
伝送用配線、51,52,60……接地用配線、
53……電源用配線、54,72……スルーホー
ル、55……リードフレーム、70……枠状のア
ルミナ基板。
用容器の平面図、第2図は第1図のA−A線断面
図、第3図は従来の半導体集積回路容器の上面図
、第4図は本考案の第2の実施例を示す半導体集
積回路用容器の部分平面図、第5図は本考案の第
3の実施例を示す半導体集積回路用容器の部分平
面図、第6図は第5図のB−B線断面図である。 21……第1層基板、22……第2層基板、2
3,61,71……接地用金属層、30……Ga
Asの半導体チツプ、31……信号用パツド、3
2,33……接地用パツド、34……電源用パツ
ド、40……ボンデイングワイヤ、50……信号
伝送用配線、51,52,60……接地用配線、
53……電源用配線、54,72……スルーホー
ル、55……リードフレーム、70……枠状のア
ルミナ基板。
Claims (1)
- 【実用新案登録請求の範囲】 (1) (a) 基板上に形成される複数の信号伝送用
配線と、 (b) 該信号伝送用配線とワイヤボンデイング
により接続される半導体チツプの信号用パツドと
、 (c) 前記信号伝送用配線の間に形成される接
地用配線と、 (d) 該接地用配線とワイヤボンデイングによ
り接続されると共に、前記信号用パツド間に形成
される前記半導体チツプの接地用パツドと、 (e) 前記接地用配線を一括して接地する接地
用金属層を具備することを特徴とする半導体集積
回路用容器。 (2) (a) 第1層基板と、 (b) 該第1層基板上に形成される接地用金属
層と、 (c) 該接地用金属層上に形成される第2層基
板と、 (d) 該第2層基板上に形成される複数の信号
伝送用配線と、 (e) 該信号伝送用配線とワイヤボンデイング
により接続される半導体チツプの信号用パツドと
、 (f) 前記信号伝送用配線の間に形成される接
地用配線と、 (g) 該接地用配線とワイヤボンデイングによ
り接続されると共に、前記信号用パツド間に形成
される前記半導体チツプの接地用パツドと、 (h) 前記接地用配線と、前記第1層基板と前
記第2層基板間に形成される接地用金属層とを電
気的に接続するスルーホールとを具備することを
特徴とする半導体集積回路用容器。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990011553U JP2502994Y2 (ja) | 1990-02-09 | 1990-02-09 | 半導体集積回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990011553U JP2502994Y2 (ja) | 1990-02-09 | 1990-02-09 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03102747U true JPH03102747U (ja) | 1991-10-25 |
JP2502994Y2 JP2502994Y2 (ja) | 1996-06-26 |
Family
ID=31515076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990011553U Expired - Lifetime JP2502994Y2 (ja) | 1990-02-09 | 1990-02-09 | 半導体集積回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2502994Y2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5693350A (en) * | 1979-12-26 | 1981-07-28 | Mitsubishi Electric Corp | Armor of semiconductor device |
JPS6037753A (ja) * | 1983-08-10 | 1985-02-27 | Nec Corp | 半導体装置用パツケ−ジ |
JPS63188963A (ja) * | 1987-01-31 | 1988-08-04 | Sumitomo Electric Ind Ltd | 半導体素子搭載用パツケ−ジ |
JPH01191433A (ja) * | 1988-01-26 | 1989-08-01 | Fujitsu Ltd | 集積回路素子 |
-
1990
- 1990-02-09 JP JP1990011553U patent/JP2502994Y2/ja not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5693350A (en) * | 1979-12-26 | 1981-07-28 | Mitsubishi Electric Corp | Armor of semiconductor device |
JPS6037753A (ja) * | 1983-08-10 | 1985-02-27 | Nec Corp | 半導体装置用パツケ−ジ |
JPS63188963A (ja) * | 1987-01-31 | 1988-08-04 | Sumitomo Electric Ind Ltd | 半導体素子搭載用パツケ−ジ |
JPH01191433A (ja) * | 1988-01-26 | 1989-08-01 | Fujitsu Ltd | 集積回路素子 |
Also Published As
Publication number | Publication date |
---|---|
JP2502994Y2 (ja) | 1996-06-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |