JPH0260237U - - Google Patents
Info
- Publication number
- JPH0260237U JPH0260237U JP1988139711U JP13971188U JPH0260237U JP H0260237 U JPH0260237 U JP H0260237U JP 1988139711 U JP1988139711 U JP 1988139711U JP 13971188 U JP13971188 U JP 13971188U JP H0260237 U JPH0260237 U JP H0260237U
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- terminal conductor
- conductive substrate
- semiconductor piece
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005219 brazing Methods 0.000 claims 6
- 239000000463 material Substances 0.000 claims 5
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第1図a,bは本考案の一実施例のパワーモジ
ユールを示し、aは平面図、bは右側面図、第2
図a,bは従来のパワーモジユールを示し、aは
平面図、bは右側面図、第3図a,b、第4図a
,bはそれぞれ本考案の異なる実施例のパワーモ
ジユールを示し、いずれもaは平面図、bは右側
面図である。
1:半導体片、2:エミツタ端子導体、3:ゲ
ート端子導体、4:容器、51:エミツタ引出し
部、52:ゲート引出し部、7,71:Al線、
8:回路部品、9:中継導体、12:導電性基板
、22,23,24:絶縁板。
Figures 1a and 1b show a power module according to an embodiment of the present invention, where a is a plan view, b is a right side view, and the second
Figures a and b show conventional power modules, where a is a plan view, b is a right side view, Figures 3 a and b, and Figure 4 a.
, b respectively show power modules of different embodiments of the present invention, in which a is a plan view and b is a right side view. 1: Semiconductor piece, 2: Emitter terminal conductor, 3: Gate terminal conductor, 4: Container, 51: Emitter drawer part, 52: Gate drawer part, 7, 71: Al wire,
8: circuit component, 9: relay conductor, 12: conductive substrate, 22, 23, 24: insulating plate.
Claims (1)
それぞれ半導体片の電極と導線を介して接続され
る主端子導体と補助端子導体が導電性基板に絶縁
板を介して固着されるものにおいて、主端子導体
および補助端子導体に互いに近接した個所が設け
られ、両近接個所の双方に回路部品が、半導体片
を導電性基板にろう付けするためのろう材と同種
のろう材を用いてろう付けされ、その回路部品が
他の端子導体上の回路部品と、半導体片の電極と
端子導体とを接続するための導線と同種の導線に
よつて接続されたことを特徴とする半導体装置。 (2) 導電性基体上に半導体片がろう付けされ、
それぞれ半導体片の電極と導線を介して接続され
る主端子導体と補助端子導体が導電性基板に絶縁
板を介して固着されるものにおいて、主端子導体
および補助端子導体に互いに近接した個所が設け
られ、一方の端子導体の近接個所に回路部品が、
半導体片を導電性基板にろう付けするためのろう
材と同種のろう材を用いてろう付けされ、その回
路部品が他の端子導体と、半導体片の電極と端子
導体とを接着するための導線と同種の導線によつ
て接続されたことを特徴とする半導体装置。 (3) 導電性基体上に半導体片がろう付けされ、
それぞれ半導体片の電極と導線を介して接続され
る主端子導体と補助端子導体が導電性基板に絶縁
板を介して固着されるものにおいて、主端子導体
および補助端子導体のほかに中継導体が両端子導
体の一部にそれぞれ近接して導電性基板に絶縁し
て固着され、中継導体には少なくとも一つの回路
部品が、半導体片を導電性基板にろう付けするた
めのろう材と同種のろう材を用いてろう付けされ
、その回路部品が端子導体と、半導体片の電極と
端子導体とを接続するための導線と同種の導線に
よつて接続されたことを特徴とする半導体装置。[Claims for Utility Model Registration] (1) A semiconductor piece is brazed on a conductive substrate,
In a device in which a main terminal conductor and an auxiliary terminal conductor, each connected to an electrode of a semiconductor piece via a conductor wire, are fixed to a conductive substrate via an insulating plate, the main terminal conductor and the auxiliary terminal conductor are provided with points close to each other. A circuit component is brazed to both adjacent locations using the same type of brazing material used to braze the semiconductor chip to the conductive substrate, and the circuit component is connected to the circuit component on the other terminal conductor. and a conductor wire of the same type as the conductor wire for connecting the electrode of the semiconductor piece and the terminal conductor. (2) A semiconductor piece is brazed onto a conductive substrate,
In a device in which a main terminal conductor and an auxiliary terminal conductor, each connected to an electrode of a semiconductor piece via a conductor wire, are fixed to a conductive substrate via an insulating plate, the main terminal conductor and the auxiliary terminal conductor are provided with points close to each other. circuit components near one terminal conductor.
Conductive wire that is brazed using the same kind of brazing material as the brazing material used to braze a semiconductor piece to a conductive substrate, and that is used to bond the circuit component to other terminal conductors and the electrode of the semiconductor piece and the terminal conductor. A semiconductor device characterized in that it is connected by the same type of conducting wire. (3) A semiconductor piece is brazed onto a conductive substrate,
In the case where the main terminal conductor and auxiliary terminal conductor, which are connected to the electrode of the semiconductor piece through the conductor wire, are fixed to the conductive substrate via an insulating plate, in addition to the main terminal conductor and the auxiliary terminal conductor, the relay conductor is connected at both ends. The intermediate conductor is insulated and fixed to the conductive substrate in close proximity to each of the child conductors, and at least one circuit component is attached to the relay conductor using a brazing material of the same type as the brazing material for brazing the semiconductor piece to the conductive substrate. A semiconductor device characterized in that the circuit components are connected by a terminal conductor and a conductor wire of the same type as a conductor wire for connecting an electrode of a semiconductor piece and a terminal conductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988139711U JPH0648874Y2 (en) | 1988-10-26 | 1988-10-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988139711U JPH0648874Y2 (en) | 1988-10-26 | 1988-10-26 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0260237U true JPH0260237U (en) | 1990-05-02 |
JPH0648874Y2 JPH0648874Y2 (en) | 1994-12-12 |
Family
ID=31403226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988139711U Expired - Lifetime JPH0648874Y2 (en) | 1988-10-26 | 1988-10-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0648874Y2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0434741U (en) * | 1990-07-18 | 1992-03-23 | ||
JPH07240497A (en) * | 1993-09-15 | 1995-09-12 | Internatl Rectifier Corp | Power semiconductor module and insulation metal substrate that is used for it |
-
1988
- 1988-10-26 JP JP1988139711U patent/JPH0648874Y2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0434741U (en) * | 1990-07-18 | 1992-03-23 | ||
JPH07240497A (en) * | 1993-09-15 | 1995-09-12 | Internatl Rectifier Corp | Power semiconductor module and insulation metal substrate that is used for it |
Also Published As
Publication number | Publication date |
---|---|
JPH0648874Y2 (en) | 1994-12-12 |
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