JPH01215121A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPH01215121A JPH01215121A JP63039961A JP3996188A JPH01215121A JP H01215121 A JPH01215121 A JP H01215121A JP 63039961 A JP63039961 A JP 63039961A JP 3996188 A JP3996188 A JP 3996188A JP H01215121 A JPH01215121 A JP H01215121A
- Authority
- JP
- Japan
- Prior art keywords
- phase detector
- lpf
- pll
- lock
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract 3
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、テレビジョン受信機の映像中間周波処理部（
以下ＶＩＦ部と呼ぶ）に適用のＰＬＬ回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video intermediate frequency processing section (
The present invention relates to a PLL circuit applied to a VIF section (hereinafter referred to as a VIF section).
従来の技術
昨今、半導体集積回路技術の進歩によって、テレビジョ
ン受信機のＶＩＦ部に、ｖＣＯ内蔵型ＰＬＬ映像同期検
波回路が用いられるようになってきた。2. Description of the Related Art Recently, with the advancement of semiconductor integrated circuit technology, PLL video synchronous detection circuits with a built-in vCO have come to be used in the VIF section of television receivers.
これにより、映像の歪み（ＤＧ、ＤＰ等）やインターキ
ャリア方式に起因する音声バズ等のレベルも、かなり大
幅に改善されてきた。As a result, the level of video distortion (DG, DP, etc.) and audio buzz caused by the intercarrier system has been significantly improved.
このようなＰＬＬ映像同期検波回路のＰＬＬ部は、第２
図に示すような構成であった。第２図において、１は位
相検波器入力、２は位相検波器（または、位相比較器）
、３は低域フィルタ（ＬＰＦ）、４は電圧制御発振器、
５はＰＬＬロック検出器、６はロック検出器入力、７は
ｖＣＯ制御端子、８．９．１１はＬＰＦを構成する抵抗
、１０はＬ Ｐ Ｆ’を構成する容量、１２はＬＰＦ切
換端子゛、１３はＬＰＦ切換用スイッチトランジスタで
ある。The PLL section of such a PLL video synchronous detection circuit has a second
The configuration was as shown in the figure. In Figure 2, 1 is the phase detector input, 2 is the phase detector (or phase comparator)
, 3 is a low pass filter (LPF), 4 is a voltage controlled oscillator,
5 is a PLL lock detector, 6 is a lock detector input, 7 is a vCO control terminal, 8.9.11 is a resistor that constitutes an LPF, 10 is a capacitor that constitutes an LPF', 12 is an LPF switching terminal, 13 is a switch transistor for LPF switching.
このような従来構成例において、ロック検出回路５によ
りＰＬＬのロック、非ロツク状態を検出し、非ロックの
時は、トランジスタ１３がオフとなり、端子１２を開放
し、抵抗Ｒ１１がＬＰＦ３の構成要素として入るので、
ＬＰＦ３が高帯域になり、妨害信号除去特性は悪くなる
が、プルインレンジが広（なるので、ＰＬＬがロックし
やすくなる。逆にロック時は、トランジスタ１３がオン
となり、端子１２はトランジスタ１３のオン抵抗（ＲＳ
ＡＴ 、 ＲＳＡＴ ＜Ｒ１１）で接地されるため、抵
抗Ｒ１＋がトランジスタ１３のオン抵抗Ｒ９Ａ□で側路
され、ＬＰＦ３が狭帯域となるので、プルインレンジは
狭くなるが、妨害信号除去特性が良くなり、良質の検波
出力を得ることができる。In such a conventional configuration example, the lock detection circuit 5 detects whether the PLL is locked or not, and when the PLL is not locked, the transistor 13 is turned off, the terminal 12 is opened, and the resistor R11 acts as a component of the LPF 3. Because I'm entering
The LPF 3 becomes high band, and the interference signal removal characteristics deteriorate, but the pull-in range becomes wide (so that the PLL locks easily. Conversely, when locked, the transistor 13 turns on, and the terminal 12 turns on the transistor 13. Resistance (RS
AT, RSAT < R11), the resistor R1+ is bypassed by the on-resistance R9A□ of the transistor 13, and the LPF3 becomes a narrow band, so the pull-in range becomes narrower, but the interference signal removal characteristics improve. Good quality detection output can be obtained.
発明が解決しようとする課題
このような従来の構成では、トランジスタ１３の飽和が
不十分なため、端子１２に不要信号が乗ったり、飽和抵
抗（Ｒ５ＡＴ）がばらついたりして、ロック時のＬＰＦ
の伝達関数（Ｆ （ｓ） ）が変動し、良質な検波出力
が得にくかった。さらに、ＩＣ化されたＰＬＬ回路にお
いては、２端子（７゜１２）と周辺部品（Ｒｓ 、 Ｒ
ｈｏ、 Ｒ＋＋）を必要とし、周辺回路の合理化等への
障害にもなってきた。Problems to be Solved by the Invention In such a conventional configuration, the saturation of the transistor 13 is insufficient, so an unnecessary signal is applied to the terminal 12, and the saturation resistance (R5AT) varies, causing the LPF to
The transfer function (F(s)) fluctuated, making it difficult to obtain a high-quality detection output. Furthermore, in an IC-based PLL circuit, two terminals (7°12) and peripheral components (Rs, R
HO, R++) and has become an obstacle to rationalization of peripheral circuits.
本発明は、このような問題点を解決するもので、ロック
時のＬＰＦの伝達関数の安定度とＩＣ化した時の端子及
び周辺部品の削減を目的とするものである。The present invention is intended to solve these problems, and aims to improve the stability of the LPF transfer function during locking and reduce the number of terminals and peripheral components when integrated into an IC.
課題を解決するための手段
この問題点を解決するために本発明は、位相検波器の変
換利得（μ）を変化させ、ＬＰＦの伝達関数は変化させ
ないようにしたものである。Means for Solving the Problem In order to solve this problem, the present invention changes the conversion gain (μ) of the phase detector, but does not change the transfer function of the LPF.
作用
この構成により、前記従来例の問題点を解決しつつ、プ
ルインレンジや妨害信号除去特性を変化させ、前記従来
例と同等のロック、非ロツク時の特性を得ることができ
、テレビジョン受像機のＶＩＦ処理に好適なＰＬＬ回路
を実現することができる。Operation With this configuration, while solving the problems of the conventional example, it is possible to change the pull-in range and interference signal removal characteristics, and obtain lock and unlock characteristics equivalent to those of the conventional example, making it possible to improve the television receiver. A PLL circuit suitable for VIF processing can be realized.
実施例
第１図は本発明の一実施例によるＰＬＬ回路のブロック
図であり、第１図において、第２図と同じものは、同一
の番号を付している。この実施例において、ＬＰＦ３は
基本構成のまま（ラグリード）伝達関数は固定で、ＰＬ
Ｌのロック、非ロツク状態に応じて、位相検波器２の変
換利得〈μ〉を変化させるものである。位相検波器２の
μを変化させるには、ＩＣ化された位相検波器において
は、電流切換回路等を用いて検波器の電流を変化させる
ことで実現可能である。Embodiment FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention. In FIG. 1, the same parts as in FIG. 2 are given the same numbers. In this example, the LPF 3 has the basic configuration (lag lead), the transfer function is fixed, and the PL
The conversion gain <μ> of the phase detector 2 is changed depending on whether L is locked or unlocked. In an IC-based phase detector, μ of the phase detector 2 can be changed by changing the current of the detector using a current switching circuit or the like.
発明の効果
以上のように、本発明によればＰＬＬの安定度の向上と
、ＩＣ化した時の端子数と周辺回路を削減という効果が
得られる。Effects of the Invention As described above, according to the present invention, it is possible to obtain the effects of improving the stability of the PLL and reducing the number of terminals and peripheral circuits when integrated into an IC.
第１図は本発明の一実施例によるＰＬＬ回路を示すブロ
ック図、第２図は従来のＰＬＬ回路を示すブロック図で
ある。
１・・・・・・位相検波器入力、２・・・・・・位相検
波器、３・・・・・・ＬＰＦ、４・・・・・・ＶＣｏ、
５・・・・・・ロック検出器、６・・・・・・ロック検
出入力、７・・・・・・ｖＣＯ制御端子、８，９．１１
・・・・・・ＬＰＦ抵抗、１０・・・・・・ＬＰＦ容量
、１２・・・・・・ＬＰＦ切換端子、１３・・・・・・
ＬＰＦＳＷトランジスタ。
代理人の氏名 弁理士 中尾敏男 ほか１名第１図
／FIG. 1 is a block diagram showing a PLL circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional PLL circuit. 1... Phase detector input, 2... Phase detector, 3... LPF, 4... VCo,
5... Lock detector, 6... Lock detection input, 7... vCO control terminal, 8, 9.11
......LPF resistance, 10...LPF capacity, 12...LPF switching terminal, 13...
LPFSW transistor. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1/
Claims (1)
得を変えることにより、プルインレンジを変化させる手
段を具備したＰＬＬ回路。A PLL circuit equipped with means for changing the pull-in range by changing the conversion gain of a phase detector depending on the locked or unlocked state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63039961A JPH01215121A (en) | 1988-02-23 | 1988-02-23 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63039961A JPH01215121A (en) | 1988-02-23 | 1988-02-23 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01215121A true JPH01215121A (en) | 1989-08-29 |
Family
ID=12567554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63039961A Pending JPH01215121A (en) | 1988-02-23 | 1988-02-23 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01215121A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408202A (en) * | 1992-06-26 | 1995-04-18 | Motorola | Phase lock loop having a lock acquisition mode and method of operation therefor |
-
1988
- 1988-02-23 JP JP63039961A patent/JPH01215121A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408202A (en) * | 1992-06-26 | 1995-04-18 | Motorola | Phase lock loop having a lock acquisition mode and method of operation therefor |
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