JPH01108890A - Yc separation circuit - Google Patents
Yc separation circuitInfo
- Publication number
- JPH01108890A JPH01108890A JP62265350A JP26535087A JPH01108890A JP H01108890 A JPH01108890 A JP H01108890A JP 62265350 A JP62265350 A JP 62265350A JP 26535087 A JP26535087 A JP 26535087A JP H01108890 A JPH01108890 A JP H01108890A
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- 238000000926 separation method Methods 0.000 title claims description 8
- 239000002131 composite material Substances 0.000 claims description 4
- 239000000284 extract Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 16
- 238000001514 detection method Methods 0.000 description 3
- 102100022002 CD59 glycoprotein Human genes 0.000 description 2
- 101000897400 Homo sapiens CD59 glycoprotein Proteins 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- Processing Of Color Television Signals (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、例えばＶＴＲ等において、コンポジット映像
信号からＹｃ （輝度）とＣｃ （Ｗ１送色）信号とを
分離して取出すＹＣ分離回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a YC separation circuit for separating and extracting Yc (luminance) and Cc (W1 color feeding) signals from a composite video signal, for example in a VTR or the like.
従来の技術
該６図は従来のＹＣ分離回路の一例のブロック図を示す
。同図において、端子１に入来したコンポジット映像信
号（例えばカラーパー信号）は、帯域フィルタ２及び後
述のフィルタ回路３を経てＣｃ倍信号されて端子４より
取出される一方、Δを遅延回路５．１日遅延回路６を経
て加算器７に供給されてここでＣｃ倍信号加算され、Ｙ
ｃ倍信号して端子８より取出される。このＹＣ分離回路
は映像信号の垂直相関を利用したものである。BACKGROUND OF THE INVENTION FIG. 6 shows a block diagram of an example of a conventional YC separation circuit. In the same figure, a composite video signal (for example, a color par signal) inputted to a terminal 1 passes through a bandpass filter 2 and a filter circuit 3, which will be described later, and is multiplied by Cc and outputted from a terminal 4. .It is supplied to the adder 7 through the 1-day delay circuit 6, where the Cc times signal is added, and the Y
The signal is multiplied by c and taken out from terminal 8. This YC separation circuit utilizes vertical correlation of video signals.
従来、垂直相関を利用したくし形フィルタは２ライン（
現在のライン情報と１日過去ライン情報）で行なってい
たが、このものは、３ライン（現在のライン情報と１日
過去のライン情報と１日未来のライン情報）で予測する
。Traditionally, comb filters using vertical correlation have two lines (
Previously, predictions were made using three lines (current line information, line information from the past day, and line information from the past day).
ここで、フィルタ回路３において、入力信号をＡ（過去
）、１日遅延回路９の出力をＢ（現在）、１日遅延回路
１０の出力をＣ（未来）とすると、信号Ａ、Ｂ、Ｃにて
上記３ラインの情報が得られる。第６図中、１１．１２
．１３は高電位検出回路（以下、ＭＡＸという）で、第
７図（Ａ）に示す構成とされており、２人力のうちのい
ずれか高い方の電位を出力する。１４．１５．１６は低
電位出力回路（以下、ＭＩＮという）で、第７図（Ｂ）
に示す構成）とされており、２人力のうちのいずれか低
い方の電位を出力する。Here, in the filter circuit 3, if the input signal is A (past), the output of the one-day delay circuit 9 is B (present), and the output of the one-day delay circuit 10 is C (future), then the signals A, B, C The above three lines of information are obtained. In Figure 6, 11.12
．． Reference numeral 13 denotes a high potential detection circuit (hereinafter referred to as MAX), which has the configuration shown in FIG. 7(A) and outputs the higher of the two potentials. 14, 15, and 16 are low potential output circuits (hereinafter referred to as MIN), as shown in Figure 7 (B).
), and outputs the lower of the two electric potentials.
いま、例えばＮＴＳＣ方式の映像信号を画面垂直方向に
みて、そのうちの３ラインを選んで分類すると、大体第
８図（Δ）〜（Ｃ）に示す３つのパターンになる。同図
（Δ）はフラットパターン、同図（Ｂ）はステップパタ
ーン、同図（Ｃ）はパルスパターンである。ここで、ｎ
は任意のラスタの１点（現在）、（ｎ−１）は任意のラ
スタの１ライン上の点（過去）、（ｎ ＋ １ ’）は
任意のラスタの１ライン下の点（未来）である。例えば
Ｃｃ倍信号ついて考えると、サブキャリアの周波数ｆｓ
ｃは、ｆｓｃ＝ （” ５／２ ）ｆ＋−＋ （ｆＨは
水平走査周波数）であるから、垂直相関がある場合はラ
イン毎に交番するパターン即ちパルスパターン（第８図
（Ｃ））であるということがいえる。For example, if an NTSC video signal is viewed in the vertical direction of the screen and three lines are selected and classified, the three patterns shown in FIG. 8 (Δ) to (C) will be obtained. The figure (Δ) shows a flat pattern, the figure (B) shows a step pattern, and the figure (C) shows a pulse pattern. Here, n
is one point on any raster (current), (n-1) is a point one line above any raster (past), (n + 1') is a point one line below any raster (future) be. For example, considering the Cc multiplied signal, the subcarrier frequency fs
Since c is fsc = (''5/2)f+-+ (fH is the horizontal scanning frequency), if there is a vertical correlation, it is a pattern that alternates for each line, that is, a pulse pattern (Figure 8 (C)). That can be said.
このパルスパターンが従来の２ライン形では得られなか
ったパターンである。This pulse pattern is a pattern that could not be obtained with the conventional two-line type.
第９図は第６図中のフィルタ回路３の基本動作を説明す
るための図を示す。例えば、ＭＡＸＩＩにて信号Ａ、Ｂ
のうちの大の方の電位を出力し、ＭＡＸ１２にて信号Ａ
、Ｂのうちの大の方の電位を出力し、ＭＩＮ１４にてＭ
ＡＸｌｌの出力とＭＡＸ１２の出力とのうちの小の方の
電位Ｘ（−）を出力し、Ｘ（＋）＝Ｍ （Ｎ （Ｂ、Ｍ
ＡＸ （Ａ、Ｃ））と記される。同様にして、ＭＩＮ１
５にて信号Ａ。FIG. 9 shows a diagram for explaining the basic operation of the filter circuit 3 in FIG. 6. For example, in MAXII, signals A and B
Outputs the larger potential of the two, and outputs the signal A at MAX12.
, B, and outputs the potential of M at MIN14.
The smaller potential X(-) of the output of AXll and the output of MAX12 is output, and X(+)=M (N (B, M
It is written as AX (A, C)). Similarly, MIN1
Signal A at 5.
Ｂのうちの小の方の電位を出力し、ＭＩＮ１６にて信号
Ｂ、Ｃのうちの小の方の電位を出力し、ＭＡＸ１３にて
ＭＩＮ１５の出力とＭＩＮ１６の出力とのうちの大の方
の電位×（−）出力し、×（−）＝ＭＡＸ （Ｂ、Ｍ
ＩＮ （Ａ、Ｃ）’）と記される。Outputs the smaller potential of signals B and C at MIN16, outputs the smaller potential of signals B and C at MAX13, and outputs the larger potential of the output of MIN15 and the output of MIN16 at MAX13. Output potential x (-), x (-) = MAX (B, M
It is written as IN (A, C)').
信号ｘ（＋） 、ｘ（−１は加算器１７にて加算され、
１／２回路１８にてレベルを１７２にされてＣｃ＝１／
２ （Ｘ（１） ＋×（−））とされる。なお、この回
路では、Ｃｃ倍信号先に得る構成であるため、現在のラ
インの信号を反転したｆｒ語を用いて演等する。The signals x(+) and x(-1 are added in an adder 17,
The level is set to 172 in the 1/2 circuit 18 and Cc=1/
2 (X(1) +×(-)). In this circuit, since the Cc multiplied signal is obtained first, the signal of the current line is performed using the fr word which is an inversion of the signal.
この場合、フィルタ回路３の伝達関数は、１／２（Ｂ＋
ＭＩＤ （Ａ、Ｂ、Ｃ））と記される。ここに、ＭＩＤ
（Ａ、Ｂ、Ｃ）は信号Ａ、Ｂ、Ｃの３人力に対して２
番目に高いデータを出力する関数である。従って、第９
図に示す４つパターンに対して図示のようなＣｃ倍信号
得られる。In this case, the transfer function of the filter circuit 3 is 1/2(B+
MID (A, B, C)). Here, M.I.D.
(A, B, C) is 2 for the 3 human power of signals A, B, C.
This is a function that outputs the highest data. Therefore, the ninth
For the four patterns shown in the figure, Cc multiplied signals as shown are obtained.
発明が解決しようとする問題点
第６図に示す従来回路は、例えば第１０図（Ａ）に示す
マルチバーストの様な白黒の繰返しによる縦縞の画柄を
表示する場合、同図（Ｂ）に示すように画像の上端及び
下端にクロスカラー及びＹｃ低信号ボケを生じる問題点
があった。つまり、第１０図（Ａ）に示すように８から
下にｗ１縞が存在する場合、上端の３ラインの情報は第
１１図（Ａ＞に示すようにＡ−０，Ｂ−Ｃ−１となり、
Ｃｃ倍信号作るために８を反転するので、第１１図（Ｂ
）に示すようにＡ−０，８−−１，Ｃ＝１となる。Problems to be Solved by the Invention The conventional circuit shown in FIG. 6, for example, when displaying a pattern of vertical stripes by repeating black and white like the multi-burst shown in FIG. 10(A), the conventional circuit shown in FIG. As shown, there was a problem that cross color and Yc low signal blurring occurred at the upper and lower ends of the image. In other words, if there is a w1 stripe below 8 as shown in Figure 10 (A), the information on the top three lines will be A-0, B-C-1 as shown in Figure 11 (A>). ,
Since 8 is inverted to create a Cc multiplied signal, Figure 11 (B
), A-0, 8--1, C=1.
従って、伝達関数＝１／２ （Ｂ＋ＭＩＤ （Ａ、Ｂ。Therefore, transfer function = 1/2 (B + MID (A, B.
Ｃ））から（−Ｂ＋Ａ）／２＝１／２がＣ，ｃ信号とし
て取出され、本来色が付いてはならない部分に色が付い
てしまう（クロスカラー）問題点かありた。一方、Ｙｃ
低信号Ｙｃ ＝ １−１／２＝１／２のように振幅が１
／２となり、ボケでしまう問題点があった。There was a problem in that (-B+A)/2=1/2 from C)) was extracted as C and c signals, and colors were added to areas that should not be colored (cross color). On the other hand, Yc
Low signal Yc = 1-1/2 = 1/2 so that the amplitude is 1
/2, which caused the problem of blurring.
問題点を解決するための手段
第１図において、加算器１９．１／２回路２０は過去ラ
インの情報と未来ラインの情報との平均の信号を得る回
路、ＭＡＸ２１．２４．ＭＩＮ２２．２３、加算器２５
は、該平均信号と不要信号成分の少ない色信号とに対し
て、同符号の場合はいずれか小さいレベルの信号を、異
符号の場合はレベルに関係なく零を夫々前る回路、減算
器２６は上記不要信号成分の少ない色信号から該いずれ
か小さいレベルの信号又は該零の信号を減算して不要信
号成分の更に少ない色信号を得る回路の各−実施例であ
る。Means for Solving the Problems In FIG. 1, the adder 19.1/2 circuit 20 is a circuit that obtains the average signal of past line information and future line information, MAX21.24. MIN22.23, adder 25
is the subtracter 26, which is a circuit that, for the average signal and a color signal with few unnecessary signal components, sends a signal of a smaller level if they have the same sign, and a signal of a smaller level if they have different signs, regardless of the level. These are embodiments of a circuit for obtaining a color signal with even less unnecessary signal components by subtracting either the signal of the lower level or the zero signal from the color signal with less unnecessary signal components.
作用
従来回路で得られた不要信号成分の少ない色信号（Ｃｃ
’）（エラー成分含む）及び前記平均信号をＭＡＸ、Ｍ
ＩＮ、加算器、減算器からなる演算回路で演算すること
により、不要信号成分の更に少ない色信号（Ｃｃ ）を
得る。特に、フラットパターンでＡ＝１．Ｂ−１／２．
Ｃ−０の場合、及び、ステップパターンでＡ＝８−１．
０＝Ｏの場合、信号Ｃｃを零にでき、画像上端、下端に
クロスカラーやＹｃ低信号ボケを生じることはない。Effect Color signal (Cc
') (including error components) and the average signal MAX, M
A color signal (Cc) with even fewer unnecessary signal components is obtained by performing calculations in an arithmetic circuit consisting of an IN, an adder, and a subtracter. In particular, A=1 in a flat pattern. B-1/2.
In the case of C-0, and in the step pattern, A=8-1.
When 0=O, the signal Cc can be made zero, and cross color or Yc low signal blurring will not occur at the top and bottom edges of the image.
実施例
第１図は本発明回路の第１実施例のブロック図を示し、
同図中、第６図と同一部分には同一番号を付してその説
明を省略する。なお、同図において一点鎖線で包囲した
部分は第６図と同一である。Embodiment FIG. 1 shows a block diagram of a first embodiment of the circuit of the present invention,
In this figure, the same parts as in FIG. 6 are given the same numbers and their explanations will be omitted. In this figure, the portion surrounded by a dashed line is the same as in FIG. 6.
第１図において、信号へと信号Ｃとは加算器１９で加算
され、１／２回路２０でレベルを１／２にされて信号り
とされる。なお、１／２回路１８の出力信号を本発明の
出力搬送色信号Ｃｃと区別するために、信号Ｃｃ’ と
する。信号Ｃｃ’ と信号りの反転された信号とはＭＡ
Ｘ２１にてその電位の高い方を取出され、ＭＩＮ２２に
て零と比較されてその電位の低い方を取出される。一方
、信号Ｃｃ’ と信号りの反転された信号とはＭＩＮ２
３にてその電位の低い方を取出され、ＭＡＸ２４にて零
と比較されてその電位の高い方を取出される。ＭＩＮ２
２の出力信号とＭＡＸ２４の出力信号とは加算器２５に
して加算されて信号Ｅとされ、減算器２６にて信号Ｃｃ
’から減算されてＣｃ倍信号して端子４より取出される
。In FIG. 1, a signal C is added to the signal by an adder 19, and the level is halved by a 1/2 circuit 20 to produce a signal. Note that the output signal of the 1/2 circuit 18 is referred to as a signal Cc' in order to distinguish it from the output carrier color signal Cc of the present invention. The signal Cc' and the inverted signal are MA
The higher potential is extracted at X21, compared with zero at MIN22, and the lower potential is extracted. On the other hand, the signal Cc' and the inverted signal are MIN2
The lower potential is extracted at step 3, compared with zero at MAX 24, and the higher potential is extracted. MIN2
The output signal of MAX24 and the output signal of MAX24 are added by an adder 25 to form a signal E, and a subtracter 26 adds a signal Cc.
' is subtracted from Cc and taken out from terminal 4 as a signal multiplied by Cc.
ここで、第８図に示す各パターンから主なものを選び、
信号Ａ、Ｂ、Ｃ夫々についてｒＯＪ ＭＪｒ１／２Ｊ
ｒ−１Ｊの組合せで考えられるパターンと、信号Ｃ
ｃ’ 、Ｄ、Ｅ、Ｃｃ、Ｙｃ、Ｙｃ’（第６図に示す端
子８より取出されるＹｃ低信号との関係を第２図に示す
。Here, choose the main one from each pattern shown in Figure 8,
rOJ MJr1/2J for each of signals A, B, and C
Possible patterns of r-1J combinations and signal C
c', D, E, Cc, Yc, Yc' (The relationship with the Yc low signal taken out from the terminal 8 shown in FIG. 6 is shown in FIG. 2).
例えば、第２図の※＋ＩＩＩに示す如く、フラットパタ
ーンでＡ＝１．８＝１／２．Ｃ＝Ｏのときく過去、現在
、未来の各ライン情報が１．１／２゜０の順で連続して
変化しているのは、縦縞が垂直方向に傾斜しているとみ
るのが一般的であり、信号Ｃｃは零を出力するのが望ま
しい）、第６図に示す従来回路では信号Ｃｃ’は一１／
４になってクロスカラーを生じてしまうが、本発明回路
では零となってクロスカラーを生じることはない。−方
、信号Ｙｃについても従来回路の１／４に対して１／２
とし得るのでボケを押え得る。For example, as shown in *+III in Figure 2, in a flat pattern A=1.8=1/2. The reason why the past, present, and future line information when C=O changes continuously in the order of 1.1/2°0 is generally considered to be because the vertical stripes are tilted in the vertical direction. In the conventional circuit shown in FIG. 6, the signal Cc' is 1/1/
However, in the circuit of the present invention, it becomes zero and does not cause cross color. - On the other hand, the signal Yc is also 1/2 compared to 1/4 of the conventional circuit.
This can reduce the blur.
又、第２図の※２１１１１に示す如く、ステップパター
ンでＡ＝８＝１．０＝Ｏのとき（マルチバーストの様な
信号で、信号Ｃｃは零を出力するのが望ましい）、従来
回路では信号Ｃｃ’ は−１／２になってクロスカラー
を生じるが、本発明回路では零となってクロスカラーを
生じることはない。−方、信号Ｙｃについても従来回路
の１／２に対して１とし得るのでボケを生じることはな
い。Also, as shown in *21111 in Figure 2, when A = 8 = 1.0 = O in the step pattern (it is desirable for the signal Cc to output zero in a multi-burst-like signal), the conventional circuit The signal Cc' becomes -1/2 and produces a cross color, but in the circuit of the present invention it becomes zero and does not produce a cross color. On the other hand, the signal Yc can also be set to 1 compared to 1/2 of the conventional circuit, so no blurring occurs.
なお、※１．※２ａｌ以外の欄の場合は、従来回路と相
違はない。In addition, *1. *For columns other than 2al, there is no difference from the conventional circuit.
ここで、本発明によって付加された回路の出力（信号Ｅ
）と信号Ｃｃ’、Ｄ（〜Ｄ）との関係を第３図に示す。Here, the output of the circuit added according to the present invention (signal E
) and the signals Cc', D (~D) are shown in FIG.
信号Ｃｃ’ と信号−りとが同符号の時はいずれか小さ
いレベルが取出され、異符号の時はそのレベルに関係な
く零が出力される。When the signal Cc' and the signal RI have the same sign, the smaller level is taken out, and when they have different signs, zero is output regardless of the level.
第４図は本発明回路の第２実施例の回路図を示し、同図
中、第６図、第１図と同一部分には同一番号を付してそ
の説明を省略する。同図において、１／２回路１８の出
力はＭＡＸ２７にて零と比較されてその高電位の方を取
出され、一方、加算器１９の出力は一１／２回路２８に
て極性を反転され、かつ、そのレベルを１７２にされて
ＭＡＸ２９にて零と比較されてその高電位の方を取出さ
れる。ＭＡＸ２７．２９．３０の各出力はＭＩＮ３１に
供給され、ここでこれらのレベルのうち最も低電位の方
が信号Ｅとして取出される。FIG. 4 shows a circuit diagram of a second embodiment of the circuit of the present invention, in which the same parts as in FIGS. 6 and 1 are given the same numbers and their explanations will be omitted. In the figure, the output of the 1/2 circuit 18 is compared with zero in the MAX 27 and the higher potential is taken out, while the output of the adder 19 is inverted in polarity by the 1/2 circuit 28. Then, the level is set to 172, compared with zero at MAX 29, and the higher potential is taken out. Each output of MAX27, 29, and 30 is supplied to MIN31, where the lowest potential among these levels is taken out as signal E.
このものの基本的な動作は第１実施例より容易に理解で
きるので、その説明を省略する。The basic operation of this device is easier to understand than the first embodiment, so its explanation will be omitted.
次に、第１図中１日遅延回路６をフィルタ回路３の１日
遅延回路９で兼用した本発明回路の変形例のブロック図
を第５図（Ａ）〜（Ｃ）に示す。Next, a block diagram of a modified example of the circuit of the present invention in which the one-day delay circuit 6 in FIG. 1 is also used as the one-day delay circuit 9 of the filter circuit 3 is shown in FIGS. 5(A) to 5(C).
第５図中、第１図、第６図と同一部分には同一番号を付
してその説明を省略する。In FIG. 5, the same parts as in FIGS. 1 and 6 are given the same numbers and their explanations will be omitted.
第５図（Ａ）〜（Ｃ）に示す変形例はともに、ＩＨＩ延
回路９の出力をΔｔｌ延回路５を介して加算器７に供給
する構成とすることにより、第１図中１日遅延回路６を
省略できる。これに伴って、第５図（Ａ）に示すもので
は、Δｔの遅延をともつ帯域フィルタ２２を１日遅延回
路９とＭＩＮ１５．１６、ＭＡＸｌｌ、１２との間に接
続すると共に、Δｔの遅延をもつ帯域フィルタ２３を１
１」遅延回路１０とＭＡＸ１２．ＭＩＮ１６との間に接
続する。第５図（Ｂ）に示すものでは、Δｔの遅延をも
つ帯域フィルタ２４を減算器２６と加算器７との間に接
続する。又、第５図（Ｃ）に示すものでは、八ｔの遅延
をもつ帯域フィルタ２５を１／２回路１８とＭＡＸ２１
．減算器２６との間に接続すると共に、八ｔの遅延をも
つ帯域フィルタ２６’１１／２回路２８とＭＡＸ２１．
ＭＩＮ２３との間に接続する。Both of the modified examples shown in FIGS. 5(A) to 5(C) have a configuration in which the output of the IHI delay circuit 9 is supplied to the adder 7 via the Δtl delay circuit 5, resulting in a one-day delay in FIG. The circuit 6 can be omitted. Accordingly, in the one shown in FIG. 5(A), the bandpass filter 22 with a delay of Δt is connected between the one-day delay circuit 9 and MIN15.16, MAXll, 12, and the delay of Δt is The bandpass filter 23 with
1” delay circuit 10 and MAX12. Connect between MIN16 and MIN16. In the one shown in FIG. 5(B), a bandpass filter 24 having a delay of Δt is connected between the subtracter 26 and the adder 7. In addition, in the one shown in FIG. 5(C), the bandpass filter 25 with a delay of 8t is connected to the 1/2 circuit 18 and the MAX21.
．． A bandpass filter 26'11/2 circuit 28 with a delay of 8t is connected between the subtracter 26 and the MAX21.
Connect between MIN23 and MIN23.
なお、各実施例、変形例ともにＰＡＬ方式の場合は１日
遅延回路の代りに２日遅延回路を用いる。Note that in both the embodiments and the modified examples, in the case of the PAL system, a two-day delay circuit is used instead of the one-day delay circuit.
発明の効果
本発明によれば、従来回路で得られた不要信号成分の少
ない色信号（エラー成分含む）及び過去ラインと未来ラ
インの平均信号を用いて演算回路で演算することにより
、不要信号成分の更に少ない色信号を得ることができ、
特に、白黒の繰返しによる縦縞状のマルチバーストを表
示する場合、従来回路のように画像上端、下端にクロス
カラーやＹｃ倍信号ボケを生じることはなく、高品質の
画面を得ることができる。Effects of the Invention According to the present invention, unnecessary signal components can be reduced by calculating in an arithmetic circuit using a color signal (including error components) with few unnecessary signal components obtained by a conventional circuit and an average signal of past lines and future lines. can obtain even less color signal,
In particular, when displaying a multiburst in the form of vertical stripes with repetition of black and white, a high-quality screen can be obtained without cross-color or Yc signal blurring occurring at the top and bottom edges of the image unlike in conventional circuits.
第１図は本発明回路の第１実施例のブロック図、第２図
は本発明回路及び従来回路で得られる信号を比較する図
、第３図は本発明回路で得られる信号状態を示す図、第
４図は本発明回路の第２実施例のブロック図、第５図は
本発明回路の変形例を示すブロック図、第６図は従来回
路のブロック図、第７図はＭへＸ回路、ＭＩＮ回路の回
路図、第８図は３ライン方式で得られるパターンを示す
図、第９図は従来回路のフィルタ回路で得られるＣｃ倍
信号説明する図、第１０図はマルチバーストの画像を示
す図、第１１図は従来回路で得られるマルチバーストの
パターンである。
１・・・コンポジット映像信号入力端子、２・・・帯域
フィルタ、３・・・フィルタ回路、４・・・色信号出力
端子、６．９．１０・・・１日遅延回路、７．１７゜１
９．２５・・・加算器、８・・・輝度信号出力端子、１
１．１２．１３，２１．２４．２７．２９゜３０・ＢＥ
位検出回路（ＭＡＸ） 、１４．１５゜１６．２２．２
３．３１・・・低電位検出回路（ＭＩＮ）、１８．２０
・・・１／２回路、２６・・・減算鼎、２８・・・−１
／２回路。
特許出願人 日本ビクター株式会社
第６図
第１０図 第１１図
（Ａ） （Ｂ） （Ａ） （Ｂ）第７図
第８図
（Ａ） −メ＼ヤ＋ −−−一−フラット
パターン第９図FIG. 1 is a block diagram of a first embodiment of the circuit of the present invention, FIG. 2 is a diagram comparing signals obtained by the circuit of the present invention and a conventional circuit, and FIG. 3 is a diagram showing signal states obtained by the circuit of the present invention. , FIG. 4 is a block diagram of a second embodiment of the circuit of the present invention, FIG. 5 is a block diagram showing a modification of the circuit of the present invention, FIG. 6 is a block diagram of a conventional circuit, and FIG. 7 is a block diagram of the circuit of the present invention. , a circuit diagram of the MIN circuit, Fig. 8 is a diagram showing a pattern obtained by the 3-line method, Fig. 9 is a diagram explaining the Cc multiplied signal obtained by the filter circuit of the conventional circuit, and Fig. 10 is a diagram showing a multi-burst image. The figure shown in FIG. 11 shows a multi-burst pattern obtained by the conventional circuit. 1... Composite video signal input terminal, 2... Bandpass filter, 3... Filter circuit, 4... Color signal output terminal, 6.9.10... 1 day delay circuit, 7.17° 1
9.25... Adder, 8... Luminance signal output terminal, 1
1.12.13, 21.24.27.29°30・BE
Position detection circuit (MAX), 14.15°16.22.2
3.31...Low potential detection circuit (MIN), 18.20
...1/2 circuit, 26...subtraction, 28...-1
/2 circuits. Patent applicant Victor Company of Japan Co., Ltd. Figure 6 Figure 10 Figure 11 (A) (B) (A) (B) Figure 7 Figure 8 (A) Figure 9
Claims (3)
取出された色信号を更に、過去ライン、現在ライン、未
来ラインの３ラインの情報を用いて演算することにより
不要信号成分の少ない色信号を取出すフィルタ回路を設
けられたＹＣ分離回路において、 上記過去ラインの情報と上記未来ラインの情報との平均
の信号を得、 該平均信号と上記不要信号構成の少ない色信号とに対し
て、同符号の場合はいずれか小さいレベルの信号を、異
符号の場合はレベルに関係なく零を夫々得、 上記不要信号成分の少ない色信号から該いずれか小さい
レベルの信号又は該零の信号を減算して不要信号成分の
更に少ない色信号を得る演算回路を新たに設けてなるこ
とを特徴とするＹＣ分離回路。(1) A filter that extracts a color signal with fewer unnecessary signal components by further calculating the color signal extracted from the composite video signal by a bandpass filter using information on three lines: past line, current line, and future line. A YC separation circuit provided with the circuit obtains an average signal of the information of the past line and the information of the future line, and determines whether the average signal and the color signal having less unnecessary signal composition have the same sign. is the signal with the smaller level, and in the case of opposite signs, obtains zero regardless of the level, and subtracts the signal with the smaller level or the signal with the zero from the color signal with fewer unnecessary signal components to obtain the unnecessary signal. A YC separation circuit characterized by being newly provided with an arithmetic circuit for obtaining a color signal with fewer components.
ない色信号とのうち高電位の方の信号を出力する第１の
回路と、 該平均信号と該不要信号成分の少ない色信号とのうち低
電位の方の信号を出力する第２の回路と、 上記第１の回路の出力と零レベルとのうち低電位の方の
信号と出力する第３の回路と、 上記第２の回路の出力と零レベルとのうち高電位の方の
信号を出力する第４の回路と、 該第３の回路の出力と該第４の回路の出力とを加算した
後、上記不要信号成分の少ない色信号から減算して該不
要信号成分の更に少ない色信号を得る第５の回路とを有
してなることを特徴とする特許請求の範囲第１項記載の
ＹＣ分離回路。(2) The arithmetic circuit includes a first circuit that outputs a signal with a higher potential between the average signal and the color signal with less unnecessary signal components; and the average signal and the color signal with less unnecessary signal components. a second circuit that outputs a signal with a lower potential between the output of the first circuit and the zero level; a third circuit that outputs a signal with a lower potential between the output of the first circuit and the zero level; A fourth circuit that outputs a signal with a higher potential between the output of the circuit and the zero level, and the output of the third circuit and the output of the fourth circuit are added, and then the unnecessary signal component is added. 2. The YC separation circuit according to claim 1, further comprising a fifth circuit that obtains a color signal with even less unnecessary signal components by subtracting from the color signal with less unnecessary signal components.
零レベルとのうち高電位の方の信号を出力する第１の回
路と、 該平均信号と零レベルとのうち高電位の方の信号を出力
する第２の回路と、 該不要信号成分の少ない色信号と該平均信号とのうち高
電位の方の信号を出力する第３の回路と、 上記第１の回路の出力と上記第２の回路の出力と該第３
の回路の出力とのうち最も低電位の信号を出力する第４
の回路と、 該不要信号成分の少ない色信号から該第４の回路の出力
を減算して該不要信号成分の更に少ない色信号を得る第
５の回路とを有してなることを特徴とする特許請求の範
囲第１項記載のＹＣ分離回路。(3) The arithmetic circuit includes a first circuit that outputs a signal with a higher potential between the color signal with less unnecessary signal components and a zero level, and a signal with a higher potential between the average signal and the zero level. a second circuit that outputs a signal with a higher potential of the color signal with less unnecessary signal components and the average signal; and an output of the first circuit and the above. The output of the second circuit and the third circuit
The fourth circuit outputs the lowest potential signal among the outputs of the circuit.
and a fifth circuit that obtains a color signal with even less unnecessary signal components by subtracting the output of the fourth circuit from the color signal with less unnecessary signal components. A YC separation circuit according to claim 1.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62265350A JP2569609B2 (en) | 1987-10-22 | 1987-10-22 | YC separation circuit |
| DE3854790T DE3854790T2 (en) | 1987-10-21 | 1988-10-20 | YC separation circuit for video signal processing circuit |
| US07/260,553 US4984069A (en) | 1987-10-21 | 1988-10-20 | YC separator for video signal processing circuit |
| EP92200043A EP0487511B1 (en) | 1987-10-21 | 1988-10-20 | YC separator for video signal processing circuit |
| EP88309897A EP0313372B1 (en) | 1987-10-21 | 1988-10-20 | Yc separator for video signal processing circuit |
| DE8888309897T DE3874282T2 (en) | 1987-10-21 | 1988-10-20 | YC ISOLATOR FOR A VIDEO SIGNAL PROCESSING CIRCUIT. |
| KR8813780A KR920000147B1 (en) | 1987-10-21 | 1988-10-21 | Yc separator for video signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62265350A JP2569609B2 (en) | 1987-10-22 | 1987-10-22 | YC separation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01108890A true JPH01108890A (en) | 1989-04-26 |
| JP2569609B2 JP2569609B2 (en) | 1997-01-08 |
Family
ID=17415954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62265350A Expired - Lifetime JP2569609B2 (en) | 1987-10-21 | 1987-10-22 | YC separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2569609B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03182191A (en) * | 1989-12-11 | 1991-08-08 | Matsushita Electric Ind Co Ltd | Y/c separation filter |
| JP2009132343A (en) * | 2007-12-03 | 2009-06-18 | Bridgestone Cycle Co | Brake lever adjustment device |
-
1987
- 1987-10-22 JP JP62265350A patent/JP2569609B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03182191A (en) * | 1989-12-11 | 1991-08-08 | Matsushita Electric Ind Co Ltd | Y/c separation filter |
| JP2009132343A (en) * | 2007-12-03 | 2009-06-18 | Bridgestone Cycle Co | Brake lever adjustment device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2569609B2 (en) | 1997-01-08 |
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