JP6735653B2 - ウエーハの分割方法 - Google Patents
ウエーハの分割方法 Download PDFInfo
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- JP6735653B2 JP6735653B2 JP2016207846A JP2016207846A JP6735653B2 JP 6735653 B2 JP6735653 B2 JP 6735653B2 JP 2016207846 A JP2016207846 A JP 2016207846A JP 2016207846 A JP2016207846 A JP 2016207846A JP 6735653 B2 JP6735653 B2 JP 6735653B2
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- wafer
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- dividing method
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Dicing (AREA)
- Laser Beam Processing (AREA)
- Die Bonding (AREA)
Description
実施形態1に係るウエーハの分割方法を図面を参照して説明する。図1は、実施形態1に係るウエーハの分割方法の加工対象のウエーハを示す斜視図である。図2は、実施形態1に係るウエーハの分割方法によりウエーハから分割されたデバイスチップを示す斜視図である。
実施形態2に係るウエーハの分割方法を図面を参照して説明する。図11は、実施形態2に係るウエーハの分割方法の遮蔽膜被覆ステップを示す斜視図である。図11は、実施形態1と同一部分に同一符号を付して説明を省略する。
実施形態3に係るウエーハの分割方法を図面を参照して説明する。図12は、実施形態3に係るウエーハの分割方法の遮蔽膜被覆ステップの流れを示す斜視図である。図13は、実施形態3に係るウエーハの分割方法の遮蔽膜被覆ステップ後のウエーハの要部の断面図である。図12及び図13は、実施形態1と同一部分に同一符号を付して説明を省略する。
WS 表面
WR 裏面
L 分割予定ライン
LB レーザー光線
D デバイス
DT デバイスチップ
LR 液状樹脂(液状の樹脂)
SR シート状の樹脂
SF 遮蔽膜
SFL 遮蔽膜層
ST2 遮蔽膜被覆ステップ
ST3 遮蔽膜除去ステップ
ST4 分割ステップ
Claims (4)
- 表面の分割予定ラインに区画された領域にデバイスが形成されたウエーハの分割方法であって、
ウエーハの裏面に、レーザー光線を吸収するレーザー光吸収剤が混合されている液状またはシート状の樹脂を被覆して遮蔽膜を形成する遮蔽膜被覆ステップと、
該遮蔽膜が被覆されたウエーハに裏面側からレーザー光線を該分割予定ラインに沿って照射し、アブレーション加工によって該遮蔽膜を該分割予定ラインに沿って除去する遮蔽膜除去ステップと、
該遮蔽膜除去ステップを実施した後、ウエーハの裏面側からウエーハをプラズマエッチングし、該遮蔽膜が除去された該分割予定ラインの領域をエッチングしてウエーハを個々のデバイスチップに分割する分割ステップと、を備え、
該遮蔽膜は、ダイボンド用接着剤であることを特徴とするウエーハの分割方法。 - 該遮蔽膜被覆ステップでは、液状樹脂をウエーハの裏面に被覆する被覆ステップと、該被覆した該液状樹脂を硬化させる硬化ステップと、を繰り返し、遮蔽膜層を2層以上積層させ該遮蔽膜を形成することを特徴とする請求項1に記載のウエーハの分割方法。
- 該レーザー光吸収剤は、染料、色素又は紫外線吸収剤からなることを特徴とする請求項1又は請求項2に記載のウエーハの分割方法。
- 該レーザー光吸収剤は、酸化物の微粉末または窒化物の微粉末であることを特徴とする請求項1又は請求項2に記載のウエーハの分割方法。
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