JP6471557B2 - 半導体装置および半導体装置の試験方法 - Google Patents
半導体装置および半導体装置の試験方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 202
- 238000012360 testing method Methods 0.000 title claims description 64
- 238000000034 method Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims description 55
- 230000015556 catabolic process Effects 0.000 claims description 41
- 239000012535 impurity Substances 0.000 claims description 26
- 230000003071 parasitic effect Effects 0.000 claims description 23
- 239000002344 surface layer Substances 0.000 claims description 8
- 238000010998 test method Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 74
- 238000012216 screening Methods 0.000 description 47
- 230000001681 protective effect Effects 0.000 description 27
- 238000010586 diagram Methods 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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Description
実施の形態1にかかる半導体装置について説明する。図1は、実施の形態1にかかる半導体装置の構造を示す説明図である。図1(b)には、実施の形態1にかかる半導体装置の一例として、出力段用の縦型nチャネルパワーMOSFETと、制御回路用の横型CMOS(Complementary MOS:相補型MOS)と、これらのMOSFETをサージから保護する保護素子10と、を同一の半導体基板(半導体チップ)上に設けた車載用のハイサイド型パワーICの断面構造を示す。図1(a)は保護素子10の平面レイアウトであり(アノード電極4および層間絶縁膜5を図示省略)、図1(b)の保護素子10は図1(a)の切断線A−A’における断面構造である。図1(b)には、保護素子10の、保護素子10以外のデバイスに初期不良が生じている製品を取り除くスクリーニング試験時の状態を示す。初期不良とは、製品仕様と異なる特性変化が生じていることである。
次に、実施の形態2にかかる半導体装置の構造について説明する。図3は、実施の形態2にかかる半導体装置の構造を示す説明図である。図3(a)には保護素子20の平面レイアウトを示し(アノード電極4および層間絶縁膜5を図示省略)、図3(b)には図3(a)の切断線B−B’における断面構造を示す。図3(b)は保護素子20のスクリーニング試験時の状態である。実施の形態2にかかる半導体装置に形成された保護素子20が実施の形態1の保護素子10と異なる点は、p-型アノード領域2の内部に、n+型高濃度領域11と離して、かつn+型高濃度領域11よりも外側に、p-型アノード領域2よりも不純物濃度の高いp+型高濃度領域(第4半導体領域)21を選択的に設けている点である。
次に、実施の形態3にかかる半導体装置の構造について説明する。図4は、実施の形態3にかかる半導体装置の構造を示す説明図である。図4(a)には保護素子30の平面レイアウトを示し(アノード電極4および層間絶縁膜5を図示省略)、図4(b)には図4(a)の切断線C−C’における断面構造を示す。図4(b)は保護素子30のスクリーニング試験時の状態である。実施の形態3にかかる半導体装置に形成された保護素子30が実施の形態2の保護素子20と異なる点は、p++型コンタクト領域3とn+型高濃度領域11との間に、GNDパッド7と同電位のn++型高濃度領域(以下、低電位n++型領域(第5半導体領域)とする)31を選択的に設けている点である。
2 p-型アノード領域
3 p++型コンタクト領域
4 アノード電極
5 層間絶縁膜
6 第1配線層
7 GNDパッド
8 n+型半導体層(縦型MOSFETのドレイン層、保護素子のカソード層)
9 裏面電極(縦型MOSFETのドレイン電極、保護素子のカソード電極)
10,20,30 保護素子
11 n+型高濃度領域
12,32 コンタクト電極
13 第2配線層
14a 第1pn接合
14b 第2pn接合
15a,15b 空乏層
16 p-型アノード領域のコーナー部
21 p+型高濃度領域
31 低電位n++型領域
33 npn寄生バイポーラトランジスタ
V1 デバイスの動作電圧
V2 保護素子の降伏電圧
V3 スクリーニング試験電圧
V4 デバイスの耐圧
V5 通常時における保護素子のスナップバック開始電圧
V6 スクリーニング試験時における保護素子のスナップバック開始電圧
Claims (7)
- 第1導電型の半導体基板の表面層に第2導電型の第1半導体領域を選択的に設けてなるダイオードと、
前記第1半導体領域の内部に選択的に設けられた、前記第1半導体領域よりも不純物濃度の高い第2導電型の第2半導体領域と、
前記第1半導体領域の内部に、前記第2半導体領域と離して、かつ前記第2半導体領域よりも外側に選択的に設けられた第1導電型の第3半導体領域と、
前記第2半導体領域に電気的に接続され、かつ第1電位に接続された第1電極と、
前記半導体基板に電気的に接続され、かつ前記第1電位よりも高い第2電位に接続された第2電極と、
前記第3半導体領域に電気的に接続された浮遊電位の第3電極と、
を備え、
第1導電型はn型であり、第2導電型はp型であることを特徴とする半導体装置。 - 前記第1半導体領域の内部に、前記第3半導体領域と離して、かつ前記第3半導体領域よりも外側に選択的に設けられた、前記第1半導体領域よりも不純物濃度の高い第2導電型の第4半導体領域をさらに備えることを特徴とする請求項1に記載の半導体装置。
- 前記第1半導体領域の内部の、前記第2半導体領域と前記第3半導体領域との間に選択的に設けられた第1導電型の第5半導体領域と、
前記第5半導体領域に電気的に接続され、かつ前記第1電位に接続された第4電極と、
をさらに備えることを特徴とする請求項1または2に記載の半導体装置。 - 前記ダイオードと同一の前記半導体基板に設けられた、前記ダイオードよりも耐圧の高い半導体素子をさらに備え、
前記半導体素子の特性を確認する試験時に、
前記第3電極は前記第1電位よりも高い第3電位に接続され、
前記第2電極を介して前記半導体素子に所定電圧が印加されることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。 - 前記ダイオードと同一の前記半導体基板に設けられた、前記ダイオードよりも耐圧の高い半導体素子をさらに備え、
前記半導体素子の特性を確認する試験時に、
前記第3電極は前記第1電位よりも高い第3電位に接続され、
前記第2電極を介して前記半導体素子に所定電圧が印加され、
前記第1半導体領域の不純物濃度または前記第3半導体領域の不純物濃度もしくはその両方は、前記試験に前記半導体基板、前記第1半導体領域および前記第5半導体領域からなる寄生バイポーラダイオードが前記所定電圧よりも高い電圧でスナップバックするように設定されていることを特徴とする請求項3に記載の半導体装置。 - 第1導電型の半導体基板の表面層に第2導電型の第1半導体領域を選択的に設けてなるダイオードと、前記ダイオードよりも耐圧の高い半導体素子と、を同一の前記半導体基板に備えた半導体装置の試験方法であって、
第1導電型はn型であり、第2導電型はp型であり、
前記半導体素子の特性を確認する試験時に、
前記第1半導体領域の内部に選択的に設けられた、前記第1半導体領域よりも不純物濃度の高い第2導電型の第2半導体領域に第1電位を印加し、
前記半導体基板に前記第1電位よりも高い第2電位を印加することで前記半導体素子に所定電圧を印加し、
前記第1半導体領域の内部に、前記第2半導体領域と離して、かつ前記第2半導体領域よりも外側に選択的に設けられた第1導電型の第3半導体領域に前記第1電位よりも高い第3電位を印加することを特徴とする半導体装置の試験方法。 - 前記所定電圧は、前記ダイオードが降伏する逆方向電圧よりも高いことを特徴とする請求項6に記載の半導体装置の試験方法。
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JP2015054604A JP6471557B2 (ja) | 2015-03-18 | 2015-03-18 | 半導体装置および半導体装置の試験方法 |
CN201610079602.XA CN105990334B (zh) | 2015-03-18 | 2016-02-04 | 半导体装置及半导体装置的试验方法 |
US15/041,027 US9865586B2 (en) | 2015-03-18 | 2016-02-10 | Semiconductor device and method for testing the semiconductor device |
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JP6471557B2 true JP6471557B2 (ja) | 2019-02-20 |
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JP7260153B2 (ja) * | 2019-03-29 | 2023-04-18 | ラピスセミコンダクタ株式会社 | 半導体装置、およびその製造方法 |
JP7310343B2 (ja) * | 2019-06-14 | 2023-07-19 | 富士電機株式会社 | 半導体装置 |
JP2021166949A (ja) * | 2020-04-09 | 2021-10-21 | 株式会社ユーディー | 水蒸気吸放出材料、それを用いる除湿剤および除湿方法 |
CN113466649B (zh) * | 2021-06-29 | 2022-10-25 | 西安交通大学 | 一种判断浪涌电流测试中SiC MOSFET失效原因的方法 |
CN117894792B (zh) * | 2024-03-15 | 2024-05-28 | 芯联越州集成电路制造(绍兴)有限公司 | Wat测试结构 |
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JPH0349257A (ja) | 1989-07-18 | 1991-03-04 | Nissan Motor Co Ltd | 半導体装置 |
JPH04247654A (ja) * | 1991-02-04 | 1992-09-03 | Nissan Motor Co Ltd | 入出力保護回路 |
JPH08130317A (ja) * | 1994-10-28 | 1996-05-21 | Sanken Electric Co Ltd | 抵抗性フィ−ルドプレ−トを備えた半導体装置 |
JP2882291B2 (ja) * | 1994-10-31 | 1999-04-12 | 関西日本電気株式会社 | 高耐圧ダイオード及びその製造方法 |
JP4084011B2 (ja) | 2001-09-05 | 2008-04-30 | 株式会社東芝 | 半導体装置 |
JP4228586B2 (ja) | 2002-05-21 | 2009-02-25 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
US7405913B2 (en) * | 2003-04-11 | 2008-07-29 | Fuji Electric Device Technology Co. | Semiconductor device having transistor with high electro-static discharge capability and high noise capability |
JP4390594B2 (ja) * | 2004-03-02 | 2009-12-24 | Okiセミコンダクタ株式会社 | 半導体装置の評価方法 |
TWI510130B (zh) * | 2010-09-20 | 2015-11-21 | Novatek Microelectronics Corp | 短路偵測電路、發光二極體驅動晶片、發光二極體裝置及短路偵測方法 |
JP5818099B2 (ja) * | 2012-04-27 | 2015-11-18 | 国立研究開発法人産業技術総合研究所 | 半導体装置 |
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- 2016-02-04 CN CN201610079602.XA patent/CN105990334B/zh not_active Expired - Fee Related
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US20160276333A1 (en) | 2016-09-22 |
JP2016174128A (ja) | 2016-09-29 |
CN105990334A (zh) | 2016-10-05 |
US9865586B2 (en) | 2018-01-09 |
CN105990334B (zh) | 2020-07-14 |
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