JP6444803B2 - 書込電圧生成回路及びメモリ装置 - Google Patents
書込電圧生成回路及びメモリ装置 Download PDFInfo
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- JP6444803B2 JP6444803B2 JP2015094334A JP2015094334A JP6444803B2 JP 6444803 B2 JP6444803 B2 JP 6444803B2 JP 2015094334 A JP2015094334 A JP 2015094334A JP 2015094334 A JP2015094334 A JP 2015094334A JP 6444803 B2 JP6444803 B2 JP 6444803B2
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- voltage
- write
- power supply
- external power
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
- G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Read Only Memory (AREA)
Description
20 書込電圧生成回路
22 カウンタ
25 セレクタ
26 昇圧回路
104 カラムデコーダ
105 電源端子
200 電源部
Claims (6)
- メモリセルに印加する書込電圧を生成する書込電圧生成回路であって、
外部電源電圧を受ける電源端子と、
前記外部電源電圧を昇圧して昇圧電圧を生成する昇圧回路と、
前記外部電源電圧及び前記昇圧電圧のうちの一方を選択し、選択した方の電圧を前記書込電圧として出力するセレクタと、
前記セレクタに接続され、前記外部電源電圧の電圧値に対応した周波数を有するパルス系列からなる発振信号を書込信号として生成し、前記書込信号中のパルスの数を計数して計数値を得る第1の回路と、を有し、
前記第1の回路は、書込期間の先頭から前記計数値が所定数に至るまでの間は前記外部電源電圧を前記書込電圧として出力させるように前記セレクタを制御する一方、前記計数値が前記所定数に至った後は前記昇圧電圧を前記書込電圧として出力させるように前記セレクタを制御することを特徴とする書込電圧生成回路。 - 前記第1の回路は、前記書込期間中に前記書込電圧を間欠的に繰り返し前記メモリセルに印加するタイミングを示すパルス系列を含む信号を前記書込信号として生成し、
前記書込信号中のパルスの数を計数して計数値を得るカウンタを含むことを特徴とする請求項1記載の書込電圧生成回路。 - 前記第1の回路は、前記発振信号を前記書込信号として生成する電圧制御発振器を含むことを特徴とする請求項1または2記載の書込電圧生成回路。
- 書込電圧をメモリセルに印加することによりデータの書き込みを行うメモリ装置であって、
外部電源電圧を受ける電源端子と、
前記外部電源電圧を昇圧して昇圧電圧を生成する昇圧回路と、
前記外部電源電圧の電圧値に対応した周波数を有するパルス系列からなる発振信号を書込信号として生成し、前記書込信号中のパルスの数を計数して計数値を得る書込駆動部と、
を有し、
前記書込駆動部は、書込期間の先頭から前記計数値が所定数に至るまでの間は前記外部電源電圧を前記書込電圧として選択する一方、前記計数値が前記所定数に至った後は前記昇圧電圧を前記書込電圧として選択することを特徴とするメモリ装置。 - 前記書込駆動部は、前記書込期間中において前記書込電圧を間欠的に繰り返し前記メモリセルに印加するタイミングを示すパルス系列を含む前記書込信号に応じて前記書込電圧を前記メモリセルに印加するデコーダと、前記書込電圧を生成する書込電圧生成回路と、を有し、
前記書込電圧生成回路は、
前記書込期間において前記書込信号中のパルスの数を計数して前記計数値を得るカウンタと、
前記書込期間の先頭から前記計数値が前記所定数に至るまでの間は前記外部電源電圧を選択する一方、前記計数値が前記所定数に至った後は前記昇圧電圧を前記書込電圧として選択するセレクタと、を含むことを特徴とする請求項4記載のメモリ装置。 - 前記書込電圧生成回路は、前記発振信号を前記書込信号として生成する電圧制御発振器を含むことを特徴とする請求項4または5記載のメモリ装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015094334A JP6444803B2 (ja) | 2015-05-01 | 2015-05-01 | 書込電圧生成回路及びメモリ装置 |
US15/142,988 US9887012B2 (en) | 2015-05-01 | 2016-04-29 | Write voltage generation circuit and memory apparatus |
CN201610275893.XA CN106409340B (zh) | 2015-05-01 | 2016-04-29 | 写入电压生成电路以及存储器装置 |
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JP2015094334A JP6444803B2 (ja) | 2015-05-01 | 2015-05-01 | 書込電圧生成回路及びメモリ装置 |
Publications (2)
Publication Number | Publication Date |
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JP2016212935A JP2016212935A (ja) | 2016-12-15 |
JP6444803B2 true JP6444803B2 (ja) | 2018-12-26 |
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US (1) | US9887012B2 (ja) |
JP (1) | JP6444803B2 (ja) |
CN (1) | CN106409340B (ja) |
Families Citing this family (1)
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KR102643283B1 (ko) | 2018-10-22 | 2024-03-06 | 삼성전자주식회사 | 메모리 장치의 동적 전원 제어 시스템 및 이를 적용한 메모리 장치 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07244993A (ja) * | 1994-03-08 | 1995-09-19 | Hitachi Ltd | 半導体記憶装置 |
JP3380823B2 (ja) * | 1994-06-23 | 2003-02-24 | 三菱電機エンジニアリング株式会社 | 半導体記憶装置 |
KR0142368B1 (ko) * | 1994-09-09 | 1998-07-15 | 김광호 | 불휘발성 반도체 메모리장치의 자동프로그램 회로 |
US5682346A (en) * | 1995-03-29 | 1997-10-28 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having suitable writing efficiency |
US5708387A (en) * | 1995-11-17 | 1998-01-13 | Advanced Micro Devices, Inc. | Fast 3-state booster-circuit |
JPH11328973A (ja) * | 1998-05-20 | 1999-11-30 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
US6734655B1 (en) * | 2000-06-30 | 2004-05-11 | Intel Corporation | Regulator design for inductive booster pump using pulse width modulation technique |
US7433258B2 (en) * | 2003-10-10 | 2008-10-07 | Datasecure Llc. | Posted precharge and multiple open-page RAM architecture |
JP4967452B2 (ja) * | 2006-05-18 | 2012-07-04 | 富士通セミコンダクター株式会社 | 半導体メモリ |
JP2008017567A (ja) | 2006-07-04 | 2008-01-24 | Sony Corp | 昇圧回路およびicカード |
US7468911B2 (en) * | 2006-11-02 | 2008-12-23 | Sandisk Corporation | Non-volatile memory using multiple boosting modes for reduced program disturb |
US8982631B2 (en) * | 2010-02-09 | 2015-03-17 | Micron Technology, Inc. | Programming methods and memories |
JP5407949B2 (ja) * | 2010-03-11 | 2014-02-05 | ソニー株式会社 | 不揮発性記憶装置及びデータ書き込み方法 |
JP2011222081A (ja) * | 2010-04-09 | 2011-11-04 | Toshiba Corp | 半導体記憶装置 |
JP5814961B2 (ja) * | 2013-02-26 | 2015-11-17 | 株式会社東芝 | 不揮発性半導体記憶装置 |
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- 2015-05-01 JP JP2015094334A patent/JP6444803B2/ja active Active
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2016
- 2016-04-29 US US15/142,988 patent/US9887012B2/en active Active
- 2016-04-29 CN CN201610275893.XA patent/CN106409340B/zh active Active
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Publication number | Publication date |
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JP2016212935A (ja) | 2016-12-15 |
CN106409340A (zh) | 2017-02-15 |
US20160322086A1 (en) | 2016-11-03 |
CN106409340B (zh) | 2021-07-02 |
US9887012B2 (en) | 2018-02-06 |
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