JP6416934B2 - 半導体装置およびその製造方法、並びに半導体モジュール - Google Patents
半導体装置およびその製造方法、並びに半導体モジュール Download PDFInfo
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- JP6416934B2 JP6416934B2 JP2016565789A JP2016565789A JP6416934B2 JP 6416934 B2 JP6416934 B2 JP 6416934B2 JP 2016565789 A JP2016565789 A JP 2016565789A JP 2016565789 A JP2016565789 A JP 2016565789A JP 6416934 B2 JP6416934 B2 JP 6416934B2
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- General Physics & Mathematics (AREA)
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Description
12 SiC−SBD
13 ワイヤ(ボンディング)
21 電極主端子
22 絶縁基板
25 ケース
26 カバー
27 共通エミッタ(ソース)回路パタン
28 共通エミッタ(ソース)主端子コンタクト
30 耐高電界封止材の形成領域
31 電極
32 ターミネーション領域
33 チップ外周部
34 耐高電界封止材
35 ハンダ
36 シリコーンゲル
37 回路配線金属
38 耐高電界封止材の端部
39 ターミネーション領域の幅
40 耐高電界封止材の塗布工程
41 チップを絶縁基板に接合する工程
42 ディスペンサーの塗布ノズル
43 ワイヤボンディング工程
44 ダイシング工程
45 スクライブライン
46 ウエハ
47 塗布時の横方向と縦方向の交差箇所
48 ターミネーション領域のコーナ部分
49 ウエハ特性検査工程
50 ダイサーのブレード
51 絶縁基板のベースプレートへの接合工程
52 ケース接着やゲル封入等のモジュールアセンブリ工程一式
53 チップ検査工程
54 テーパー形状
55 ウエハ状態での耐高電界封止材の塗布形状
56 電極端境界
57 ワイヤボンディングの接合部
58 ワイヤボンディング接合部のヒール
59 耐高電界封止材の電極へのオーバーラップ長
60 耐高電界封止材の凹形状
61 耐高電界封止材の凸形状
62 カーボン治具とチップ端面の耐高電界封止材の接触部
63 凹凸つきの加圧治具
64 SiCのp型不純物領域
65 SiO2膜
66 ポリイミド膜
67 ケース内の残りの空間
68 ベースプレート
69 チャネルストッパ
70 中央配置のゲート電極パッド
71 電極端部寄り配置のゲート電極パッド
Claims (13)
- ワイドギャップ半導体素子が形成された半導体チップを備え、
前記半導体チップのパタン面側のチップの周辺部に形成される耐高電界封止材の断面形状が、チップ外周端側の少なくとも一部が垂直またはそれに近い端面形状を有し、チップ内周端側では内側に向けて膜厚が減少する形状を有し、
前記ワイドギャップ半導体素子はシリコンカーバイドを含んで構成され、
チップ外周端側の少なくとも一部が垂直ないしそれに近い端面形状を有する部分が、電界緩和領域幅の最大でも1/3以下だけチップ端からリセスした構造である
ことを特徴とする半導体装置。 - 請求項1において、
前記耐高電界封止材は、ポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、およびポリエーテルアミド樹脂のうちの少なくとも一種を含んで構成される
ことを特徴とする半導体装置。 - 請求項1において、
前記耐高電界封止材の膜厚が、少なくとも50μm以上で、かつ500μm以下である
ことを特徴とする半導体装置。 - 請求項1において、
前記耐高電界封止材の比誘電率が、下地の無機材料層の比誘電率より小さく、かつ上層の封止材の比誘電率より大きい
ことを特徴とする半導体装置。 - ワイドギャップ半導体素子が形成された半導体チップを備え、
前記半導体チップのパタン面側のチップの周辺部に形成される耐高電界封止材の断面形状が、チップ外周端側の少なくとも一部が垂直またはそれに近い端面形状を有し、チップ内周端側では内側に向けて膜厚が減少する形状を有し、
チップ外周端側の少なくとも一部が垂直ないしそれに近い端面形状を有する部分が、電界緩和領域幅の最大でも1/3以下だけチップ端からリセスした構造である
ことを特徴とする半導体装置。 - ワイドギャップ半導体素子が形成された半導体チップを備えた半導体装置の製造方法であって、
前記半導体チップのパタン面側のチップの周辺部に配置する耐高電界封止材を半導体ウエハの状態で形成する工程と、
前記半導体ウエハに対して熱処理を実施する工程と、
熱処理された前記半導体ウエハに対してダイシングを実施する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項6において、
前記熱処理の温度が、200℃から400℃の範囲にある
ことを特徴とする半導体装置の製造方法。 - 請求項6において、
前記耐高電界封止材の形成工程は、ウエハのスクライブラインに沿って前記耐高電界封止材を少なくとも2つの方向から交差させて塗布する工程を含む
ことを特徴とする半導体装置の製造方法。 - ワイドギャップ半導体素子が形成された半導体チップを搭載した半導体モジュールであって、
前記半導体チップは、前記半導体チップのパタン面側のチップの周辺部に形成される耐高電界封止材の断面形状が、チップ外周端側の少なくとも一部が垂直またはそれに近い端面形状を有し、チップ内周端側では内側に向けて膜厚が減少する形状を有し、
前記ワイドギャップ半導体素子はシリコンカーバイドを含んで構成され、
チップ外周端側の少なくとも一部が垂直ないしそれに近い端面形状を有する部分が、電界緩和領域幅の最大でも1/3以下だけチップ端からリセスした構造である
ことを特徴とする半導体モジュール。 - 請求項9において、
前記耐高電界封止材は、ポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、およびポリエーテルアミド樹脂のうちの少なくとも一種を含んで構成される
ことを特徴とする半導体モジュール。 - 請求項9において、
前記耐高電界封止材の膜厚が、少なくとも50μm以上で、かつ500μm以下である
ことを特徴とする半導体モジュール。 - 請求項9において、
前記耐高電界封止材の比誘電率が、下地の無機材料層の比誘電率より小さく、かつ上層の封止材の比誘電率より大きい
ことを特徴とする半導体モジュール。 - ワイドギャップ半導体素子が形成された半導体チップを搭載した半導体モジュールであって、
前記半導体チップは、前記半導体チップのパタン面側のチップの周辺部に形成される耐高電界封止材の断面形状が、チップ外周端側の少なくとも一部が垂直またはそれに近い端面形状を有し、チップ内周端側では内側に向けて膜厚が減少する形状を有し、
チップ外周端側の少なくとも一部が垂直ないしそれに近い端面形状を有する部分が、電界緩和領域幅の最大でも1/3以下だけチップ端からリセスした構造である
ことを特徴とする半導体モジュール。
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US11538769B2 (en) * | 2018-12-14 | 2022-12-27 | General Electric Company | High voltage semiconductor devices having improved electric field suppression |
US10892237B2 (en) * | 2018-12-14 | 2021-01-12 | General Electric Company | Methods of fabricating high voltage semiconductor devices having improved electric field suppression |
US11923716B2 (en) | 2019-09-13 | 2024-03-05 | Milwaukee Electric Tool Corporation | Power converters with wide bandgap semiconductors |
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