JP6110848B2 - ガス処理方法 - Google Patents
ガス処理方法 Download PDFInfo
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- JP6110848B2 JP6110848B2 JP2014516713A JP2014516713A JP6110848B2 JP 6110848 B2 JP6110848 B2 JP 6110848B2 JP 2014516713 A JP2014516713 A JP 2014516713A JP 2014516713 A JP2014516713 A JP 2014516713A JP 6110848 B2 JP6110848 B2 JP 6110848B2
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- 238000003672 processing method Methods 0.000 title claims description 10
- 239000007789 gas Substances 0.000 claims description 178
- 238000005530 etching Methods 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 28
- 238000006243 chemical reaction Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 238000010790 dilution Methods 0.000 claims description 16
- 239000012895 dilution Substances 0.000 claims description 16
- 239000007795 chemical reaction product Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000354 decomposition reaction Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 47
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 26
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 24
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 5
- -1 ammonium fluorosilicate Chemical compound 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Description
図1は、本発明の一実施形態に係るガス処理方法を実施するための処理システムを示す概略構成図である。この処理システム1は、半導体ウエハ(以下、単にウエハと記す)Wを搬入出する搬入出部2と、搬入出部2に隣接させて設けられた2つのロードロック室(L/L)3と、各ロードロック室3にそれぞれ隣接して設けられた、ウエハWに対してPHT(Post Heat Treatment)処理を行なうPHT処理装置(PHT)4と、各PHT処理装置4にそれぞれ隣接して設けられた、ウエハWに対してCOR処理を行なうCOR処理装置(COR)5とを備えている。ロードロック室3、PHT処理装置4およびCOR処理装置5は、この順に一直線上に並べて設けられている。
本実施形態では、ウエハWの表面に存在するパターン化されたシリコン酸化膜をエッチングする。例えば、図4に示すような、熱酸化膜202を有するシリコン基板201にシャロートレンチ203を形成し、シャロートレンチ203を、TEOSを用いたCVDによりシリコン酸化膜(TEOS−SiO2膜)204で埋めたシャロートレンチアイソレーション(STI)構造のウエハWを準備し、表面に残存しているパターン状の熱酸化膜202を処理システム1によりエッチングする。
その結果、温度および反応ガスの量を基本的に変化させず、圧力を上昇させることにより、エッチング性とエッチングの形状性を両立できることが見出された。
Claims (6)
- チャンバー内に表面にパターン状のシリコン酸化膜が形成された被処理体を収容し、前記チャンバー内に反応ガスであるHFガスおよびNH3ガス、ならびに希釈ガスを供給して、これらと前記シリコン酸化膜とを反応させる処理を行い、その後、この反応により生成した反応生成物を加熱して分解除去する処理を行って、前記シリコン酸化膜をエッチングするガス処理方法であって、
前記反応させる処理の、前記チャンバー内の圧力、処理温度、ならびに前記HFガス、前記NH3ガス、および希釈ガスの流量の条件が、その後前記分解除去する処理を行ってエッチング残りが存在する所定条件である場合に、
前記反応させる処理の条件を、前記処理温度、および前記HFガスおよび前記NH3ガスの流量を前記所定条件に維持したまま、前記希釈ガスの量を前記所定条件から増加させて、前記チャンバー内の圧力を上昇させた条件にして前記反応させる処理を行い、その後前記分解除去する処理を行うことにより、前記エッチング残りを解消するとともに、垂直性の高いエッチング形状となるようにする、ガス処理方法。 - 前記チャンバー内の圧力を上昇させた条件下での前記反応させる処理の処理温度を40℃以下、前記チャンバー内の圧力を200mTorr以上とする、請求項1に記載のガス処理方法。
- 前記チャンバー内の圧力を上昇させた条件下での前記反応させる処理の処理温度を35℃以下とする、請求項2に記載のガス処理方法。
- 前記チャンバー内の圧力を上昇させた条件下での前記反応させる処理を行う際に、前記チャンバー内のHFガスの分圧が5〜50mTorr、NH3ガスの分圧が5〜50mTorr、希釈ガスの分圧が200mTorr以上となるように、前記HFガス、前記NH3ガス、および希釈ガスの流量を調整する、請求項2または請求項3に記載のガス処理方法。
- 前記チャンバー内の圧力を上昇させた条件下での前記反応させる処理を行う際に、前記チャンバー内の圧力を300mTorr以上とする、請求項2から請求項4のいずれか1項に記載のガス処理方法。
- シャロートレンチアイソレーション構造のパターン状の熱酸化膜をエッチングするものである、請求項1から請求項5のいずれか1項に記載のガス処理方法。
Priority Applications (1)
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JP2014516713A JP6110848B2 (ja) | 2012-05-23 | 2013-04-04 | ガス処理方法 |
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JP2012117990 | 2012-05-23 | ||
JP2012117990 | 2012-05-23 | ||
PCT/JP2013/060294 WO2013175872A1 (ja) | 2012-05-23 | 2013-04-04 | ガス処理方法 |
JP2014516713A JP6110848B2 (ja) | 2012-05-23 | 2013-04-04 | ガス処理方法 |
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JPWO2013175872A1 JPWO2013175872A1 (ja) | 2016-01-12 |
JP6110848B2 true JP6110848B2 (ja) | 2017-04-05 |
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Country Status (5)
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US (1) | US9384993B2 (ja) |
JP (1) | JP6110848B2 (ja) |
KR (1) | KR101707295B1 (ja) |
TW (1) | TWI600084B (ja) |
WO (1) | WO2013175872A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US10290553B2 (en) | 2015-06-24 | 2019-05-14 | Tokyo Electron Limited | System and method of determining process completion of post heat treatment of a dry etch process |
WO2017136306A1 (en) * | 2016-02-01 | 2017-08-10 | Tokyo Electron Limited | System and method of determining process completion of post heat treatment of a dry etch process |
JP6561093B2 (ja) | 2017-07-24 | 2019-08-14 | 東京エレクトロン株式会社 | シリコン酸化膜を除去する方法 |
US10607851B2 (en) | 2017-08-25 | 2020-03-31 | Micron Technology, Inc. | Vapor-etch cyclic process |
JP7113681B2 (ja) * | 2018-06-28 | 2022-08-05 | 株式会社日立ハイテク | エッチング処理方法およびエッチング処理装置 |
US10854442B2 (en) | 2018-06-29 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Orientation chamber of substrate processing system with purging function |
JP2023087228A (ja) * | 2021-12-13 | 2023-06-23 | 東京エレクトロン株式会社 | ガス処理方法およびガス処理装置 |
Family Cites Families (18)
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US7494560B2 (en) * | 2002-11-27 | 2009-02-24 | International Business Machines Corporation | Non-plasma reaction apparatus and method |
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JP4833512B2 (ja) | 2003-06-24 | 2011-12-07 | 東京エレクトロン株式会社 | 被処理体処理装置、被処理体処理方法及び被処理体搬送方法 |
JP4860219B2 (ja) * | 2005-02-14 | 2012-01-25 | 東京エレクトロン株式会社 | 基板の処理方法、電子デバイスの製造方法及びプログラム |
US7510972B2 (en) * | 2005-02-14 | 2009-03-31 | Tokyo Electron Limited | Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device |
US7622392B2 (en) * | 2005-02-18 | 2009-11-24 | Tokyo Electron Limited | Method of processing substrate, method of manufacturing solid-state imaging device, method of manufacturing thin film device, and programs for implementing the methods |
JP2007201168A (ja) * | 2006-01-26 | 2007-08-09 | Sony Corp | 自然酸化膜の除去方法及び半導体装置の製造方法 |
US7718032B2 (en) * | 2006-06-22 | 2010-05-18 | Tokyo Electron Limited | Dry non-plasma treatment system and method of using |
JP5084250B2 (ja) | 2006-12-26 | 2012-11-28 | 東京エレクトロン株式会社 | ガス処理装置およびガス処理方法ならびに記憶媒体 |
US7786016B2 (en) * | 2007-01-11 | 2010-08-31 | Micron Technology, Inc. | Methods of uniformly removing silicon oxide and a method of removing a sacrificial oxide |
JP4949091B2 (ja) * | 2007-03-16 | 2012-06-06 | 東京エレクトロン株式会社 | 基板処理装置、基板処理方法および記録媒体 |
US7899637B2 (en) * | 2007-06-13 | 2011-03-01 | Tokyo Electron Limited | Method and apparatus for creating a gate optimization evaluation library |
US8026180B2 (en) * | 2007-07-12 | 2011-09-27 | Micron Technology, Inc. | Methods of modifying oxide spacers |
US7765077B2 (en) * | 2007-09-21 | 2010-07-27 | Tokyo Electron Limited | Method and apparatus for creating a Spacer-Optimization (S-O) library |
JP5374039B2 (ja) * | 2007-12-27 | 2013-12-25 | 東京エレクトロン株式会社 | 基板処理方法、基板処理装置及び記憶媒体 |
JP4968861B2 (ja) * | 2009-03-19 | 2012-07-04 | 東京エレクトロン株式会社 | 基板のエッチング方法及びシステム |
US20110061810A1 (en) * | 2009-09-11 | 2011-03-17 | Applied Materials, Inc. | Apparatus and Methods for Cyclical Oxidation and Etching |
KR20130010362A (ko) * | 2011-07-18 | 2013-01-28 | 삼성전자주식회사 | 반도체 장치의 제조방법 |
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- 2013-04-04 JP JP2014516713A patent/JP6110848B2/ja active Active
- 2013-05-16 TW TW102117368A patent/TWI600084B/zh active
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KR101707295B1 (ko) | 2017-02-15 |
US20150079801A1 (en) | 2015-03-19 |
KR20150022773A (ko) | 2015-03-04 |
US9384993B2 (en) | 2016-07-05 |
WO2013175872A1 (ja) | 2013-11-28 |
TW201409568A (zh) | 2014-03-01 |
JPWO2013175872A1 (ja) | 2016-01-12 |
TWI600084B (zh) | 2017-09-21 |
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