JP5625063B2 - 容量性分圧器 - Google Patents
容量性分圧器 Download PDFInfo
- Publication number
- JP5625063B2 JP5625063B2 JP2012537393A JP2012537393A JP5625063B2 JP 5625063 B2 JP5625063 B2 JP 5625063B2 JP 2012537393 A JP2012537393 A JP 2012537393A JP 2012537393 A JP2012537393 A JP 2012537393A JP 5625063 B2 JP5625063 B2 JP 5625063B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitance
- voltage divider
- compensation
- parasitic capacitance
- parasitic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Description
Claims (10)
- 第1の分圧器(101)および第2の分圧器(102)を含んでいる容量性分圧器装置(100)であって、第1の寄生容量(Cp1)および第2の寄生容量(Cp2)は、前記第1の容量性分圧器(101)と前記第2の容量性分圧器(102)の間に形成されており、
前記第1の容量性分圧器(101)は、
信号のための端末(110)と、
第1の静電容量(C1)を介して、前記端末(110)が基準電位(U0)と結合しうる前記第1の静電容量(C1)と、
第2の静電容量(C2)と、
前記基準電位(U0)と結合しうる第3の静電容量(C3)であって、前記第2の静電容量(C2)が前記端末(110)と前記第3の静電容量(C3)の間に結合されていることを特徴とする前記第3の静電容量(C3)とを含み、そして、
前記第2の容量性分圧器(102)は、
第1の補償容量(C’1)を介して、前記端末(110)が前記基準電位(U0)と結合しうる前記第1の補償容量(C’1)であって、前記第1の補償容量(C’1)は、前記第1の寄生容量(Cp1)を介して前記端末(110)と更に結合されている前記第1の補償容量(C’1)と、
第2の補償容量(C’2)と、
前記基準電位(U0)と結合されうる第3の補償容量(C’3)であって、前記第2の補償容量(C’2)が、前記端末(110)と前記第3の補償容量(C’3)の間に結合されており、前記第2の寄生容量(Cp2)が、前記第2の補償容量(C’2)と結合された端末にある前記第3の補償容量(C’3)に、前記第2の静電容量(C2)と結合された端末にある前記第3の静電容量(C3)を結合している前記第3の補償容量(C’3)を含み、
前記第1の静電容量(C 1 )、前記第2の静電容量(C 2 )、前記第3の静電容量(C 3 )、前記第1の寄生容量(Cp 1 )、前記第2の寄生容量(Cp 2 )、前記第1の補償容量(C’ 1 )、前記第2の補償容量(C’ 2 )、および前記第3の補償容量(C’ 3 )は、基板に実装され、
前記基板は、前記第1の静電容量(C 1 )、前記第2の静電容量(C 2 )、および前記第3の静電容量(C 3 )が実装される第1の層を含むこと、および、前記基板は、前記第1の補償容量(C’ 1 )、前記第2の補償容量(C’ 2 )、および前記第3の補償容量(C’ 3 )が実装される第2の層を含み、前記第1の寄生容量(Cp 1 )および前記第2の寄生容量(Cp 2 )が、前記第1の層と前記第2の層の間に形成していることを特徴とする、容量性分圧器装置(100)。 - 第3の寄生容量(Cp3)を介して、前記端末(110)が前記基準電位(U0)と結合されうる前記第3の寄生容量(Cp3)を更に含み、かつ、第4の寄生容量(Cp4)を介して、前記第2の補償容量(C’2)と結合された前記端末にある前記第3の補償容量(C’3)が、前記基準電位(U0)と結合されうる前記第4の寄生容量(Cp4)を更に含むことを特徴とする、請求項1に記載の容量性分圧器装置(100)。
- 前記第3の寄生容量(Cp3)および前記第4の寄生容量(Cp4)は、それらの静電容量に関して、10%未満の差で異なることを特徴とする、請求項2に記載の容量性分圧器装置(100)。
- 前記第1の静電容量(C1)および前記第2の静電容量(C2)は、それらの静電容量に関して、10%未満の差で異なること、および、前記第1の補償容量(C’1)および前記第2の補償静電容量(C’2)は、それらの静電容量に関して、10%未満の差で異なること、および、前記第2の静電容量(C2)の半分および前記第3の静電容量(C3)は、それらの静電容量に関して、10%未満の差で異なること、および、前記第2の補償容量(C’2)の半分および前記第3の補償容量(C’3)は、それらの静電容量に関して、10%未満の差で異なることを特徴とする、請求項1〜請求項3のいずれか一項に記載の容量性分圧器装置(100)。
- 前記第1の寄生容量(Cp1)および前記第2の寄生容量(Cp2)は、それらの静電容量に関して、10%未満の差で異なること、および、前記第3の寄生容量(Cp3)および前記第4の寄生容量(Cp4)は、それらの静電容量に関して、10%未満の差で異なることを特徴とする、請求項1〜請求項4のいずれか一項に記載の容量性分圧器装置(100)。
- 前記第1の分圧器(101)は、複数の静電容量を有する容量性カスケード接続を含むこと、および、前記第2の分圧器(102)は、複数の静電容量を有する容量性カスケード接続を含むことを特徴とする、請求項1〜請求項5のいずれか一項に記載の容量性分圧器装置(100)。
- 請求項1〜請求項6のいずれか一項に記載の容量性分圧器装置(100)を含んでいるアナログ−デジタル変換器。
- 逐次比較法で作動されるように構成されることを特徴とする、請求項7に記載のアナログ−デジタル変換器。
- CMOS 2−poly 4−metal技術(CMOS=相補型金属酸化膜半導体)で実装されることを特徴とする、請求項7または請求項8に記載のアナログ−デジタル変換器。
- 第1のスイッチマトリクス(315)、第2のスイッチマトリクス(320)、SAR制御論理(325)(SAR=逐次比較レジスタ)、サンプルホールド素子(330)、およびコンパレータ(335)を更に含むことを特徴とする、請求項7〜請求項9のいずれか一項に記載のアナログ−デジタル変換器を含んでいるデジタル−アナログ変換器。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102009051830.4 | 2009-11-04 | ||
DE200910051830 DE102009051830B3 (de) | 2009-11-04 | 2009-11-04 | Kapazitiver Spannungsteiler |
PCT/EP2010/066759 WO2011054883A1 (en) | 2009-11-04 | 2010-11-03 | Capacitive voltage divider |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013510483A JP2013510483A (ja) | 2013-03-21 |
JP5625063B2 true JP5625063B2 (ja) | 2014-11-12 |
Family
ID=43707775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012537393A Expired - Fee Related JP5625063B2 (ja) | 2009-11-04 | 2010-11-03 | 容量性分圧器 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8957803B2 (ja) |
EP (1) | EP2401814B1 (ja) |
JP (1) | JP5625063B2 (ja) |
DE (1) | DE102009051830B3 (ja) |
TW (1) | TWI470938B (ja) |
WO (1) | WO2011054883A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DK2699340T3 (da) | 2011-04-18 | 2021-01-11 | Biotechflow Ltd | Indretning og fremgangsmåder til fluidbehandling og flowstyring |
EP2929359B1 (en) | 2012-12-05 | 2021-02-03 | Schneider Electric USA, Inc. | Isolated and self-calibrating voltage measurement sensor |
US9438264B1 (en) * | 2015-09-10 | 2016-09-06 | Realtek Semiconductor Corp. | High-speed capacitive digital-to-analog converter and method thereof |
US10243579B2 (en) * | 2016-12-23 | 2019-03-26 | Avnera Corporation | Programmable trim filter for successive approximation register analog to digital converter comparator |
CN111034137B (zh) * | 2017-05-22 | 2022-11-04 | 康杜实验室公司 | 具有更大增益的多级采样器 |
EP3639371A1 (en) | 2017-06-16 | 2020-04-22 | Telefonaktiebolaget LM Ericsson (PUBL) | Digital-to-analog converter |
CN108152554B (zh) * | 2018-02-02 | 2024-03-19 | 中国工程物理研究院流体物理研究所 | 一种测量同轴电缆脉冲电压的电容分压器 |
JP2019149762A (ja) * | 2018-02-28 | 2019-09-05 | 株式会社日立製作所 | 逐次比較型ad変換器およびセンサ装置 |
US10277244B1 (en) * | 2018-07-26 | 2019-04-30 | Qualcomm Incorporated | Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling |
US10812098B1 (en) * | 2019-06-27 | 2020-10-20 | Texas Instruments Incorporated | Analog-to-digital converter decision control |
CN110736866B (zh) * | 2019-11-26 | 2024-06-21 | 无锡市电力滤波有限公司 | 一种10kV电容式分压器 |
EP4142133A1 (en) * | 2021-08-30 | 2023-03-01 | Murata Manufacturing Co., Ltd. | An electrical device comprising an ac voltage divider and capacitors arranged in integrated components |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4097753A (en) * | 1976-04-02 | 1978-06-27 | International Business Machines Corporation | Comparator circuit for a C-2C A/D and D/A converter |
US4399426A (en) * | 1981-05-04 | 1983-08-16 | Tan Khen Sang | On board self-calibration of analog-to-digital and digital-to-analog converters |
JPH071870B2 (ja) * | 1984-07-31 | 1995-01-11 | 日本電気株式会社 | ディジタル/アナログ変換回路 |
US4947169A (en) * | 1989-10-24 | 1990-08-07 | Burr-Brown Corporation | Dummy/trim DAC for capacitor digital-to-analog converter |
US5272481A (en) * | 1991-07-02 | 1993-12-21 | David Sarnoff Research Center, Inc. | Successive approximation analog to digital converter employing plural feedback digital to analog converters |
US5548203A (en) * | 1994-06-29 | 1996-08-20 | Electric Power Research Institute, Inc. | Capacitor polarity-based var correction controller for resonant line conditions and large amplitude line harmonics |
JPH11195990A (ja) * | 1997-12-26 | 1999-07-21 | Motorola Kk | 信号変換装置 |
US6420988B1 (en) | 1998-12-03 | 2002-07-16 | Semiconductor Energy Laboratory Co., Ltd. | Digital analog converter and electronic device using the same |
US6204723B1 (en) | 1999-04-29 | 2001-03-20 | International Business Machines Corporation | Bias circuit for series connected decoupling capacitors |
US6583416B1 (en) * | 1999-11-15 | 2003-06-24 | Sarnoff Corporation | Uncooled IR detector array having improved temperature stability and reduced fixed pattern noise |
US6600437B1 (en) * | 2002-04-01 | 2003-07-29 | Stmicroelectronics S.R.L. | High resolution, high speed, low power switched capacitor digital to analog converter |
TW200416657A (en) * | 2003-02-24 | 2004-09-01 | Tenx Technology Inc | Lower-power-comsumption voltage generator |
JP4755558B2 (ja) | 2006-09-13 | 2011-08-24 | パナソニック株式会社 | Ad変換器およびデルタシグマad変換器 |
US20080246340A1 (en) * | 2007-04-06 | 2008-10-09 | Swisher Carl R | Battery integrated power supply (BIPS) |
US7609184B2 (en) * | 2007-11-08 | 2009-10-27 | Advantest Corporation | D-A convert apparatus and A-D convert apparatus |
-
2009
- 2009-11-04 DE DE200910051830 patent/DE102009051830B3/de not_active Expired - Fee Related
-
2010
- 2010-11-03 JP JP2012537393A patent/JP5625063B2/ja not_active Expired - Fee Related
- 2010-11-03 TW TW99137760A patent/TWI470938B/zh not_active IP Right Cessation
- 2010-11-03 EP EP10773625A patent/EP2401814B1/en not_active Not-in-force
- 2010-11-03 WO PCT/EP2010/066759 patent/WO2011054883A1/en active Application Filing
-
2012
- 2012-05-03 US US13/463,132 patent/US8957803B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2013510483A (ja) | 2013-03-21 |
TWI470938B (zh) | 2015-01-21 |
EP2401814B1 (en) | 2012-12-26 |
US20120306676A1 (en) | 2012-12-06 |
DE102009051830B3 (de) | 2011-06-30 |
TW201141072A (en) | 2011-11-16 |
US8957803B2 (en) | 2015-02-17 |
EP2401814A1 (en) | 2012-01-04 |
WO2011054883A1 (en) | 2011-05-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5625063B2 (ja) | 容量性分圧器 | |
Hsieh et al. | A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC | |
US9954549B2 (en) | Charge-sharing and charge-redistribution DAC and method for successive approximation analog-to-digital converters | |
US6784824B1 (en) | Analog-to-digital converter which is substantially independent of capacitor mismatch | |
Pelgrom et al. | Analog-to-digital conversion | |
US8159382B2 (en) | Low power converter and shutdown SAR ADC architecture | |
Huang et al. | A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer | |
EP1614219B1 (en) | Comparator offset calibration for a/d converters | |
US10348319B1 (en) | Reservoir capacitor based analog-to-digital converter | |
Kuramochi et al. | A 0.05-mm 2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS | |
Nam et al. | An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS | |
Zhang et al. | A 12-bit two-step single-slope ADC with a constant input-common-mode level resistor ramp generator | |
Cenci et al. | A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator | |
Kim et al. | A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array | |
Kim et al. | A 12-bit 200-kS/s SAR ADC with hybrid RC DAC | |
Shen et al. | A 14-bit oversampled SAR ADC with mismatch error shaping and analog range compensation | |
Zhu et al. | A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs | |
Mahdavi et al. | A new 13-bit 100MS/s full differential successive approximation register analog to digital converter (SAR ADC) using a novel compound R-2R/C structure | |
Balasubramaniam et al. | 12-bit hybrid C2C DAC based SAR ADC with floating voltage shield | |
Hou et al. | An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator | |
Long et al. | A 1.8-V 3.1 mW successive approximation ADC in system-on-chip | |
Zhang et al. | A low-power pipelined-SAR ADC using boosted bucket-brigade device for residue charge processing | |
Narasimaiah et al. | 14.5 fJ/conversion‐step 9‐bit 100‐kS/s non‐binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS | |
Jeon et al. | A 3V 12Bit 4MS/s Asynchronous SAR ADC with On-Chip 3-Step Background Calibration Using Split Structure | |
Jung et al. | A novel self-calibration scheme for 12-bit 50MS/s SAR ADC |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130709 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131002 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131009 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140107 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140212 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140611 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140723 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20140818 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140909 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140929 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5625063 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |