JP5444238B2 - 画素駆動回路 - Google Patents
画素駆動回路 Download PDFInfo
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- JP5444238B2 JP5444238B2 JP2010531588A JP2010531588A JP5444238B2 JP 5444238 B2 JP5444238 B2 JP 5444238B2 JP 2010531588 A JP2010531588 A JP 2010531588A JP 2010531588 A JP2010531588 A JP 2010531588A JP 5444238 B2 JP5444238 B2 JP 5444238B2
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- floating gate
- tft
- pixel circuit
- active matrix
- connection
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Classifications
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- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Description
有機発光ダイオード、ここでは有機金属系のLEDを含むが、有機発光ダイオードは、ポリマー、小分子、およびデンドリマーなどの材料を用いて、使用される材料に依存するさまざまな色で製造され得る。ポリマー系の有機LEDの例は、国際公開第90/13148号、国際公開第95/06400号、および国際公開第99/48160号に記載され、デンドリマー系の材料の例は、国際公開第99/21935号および国際公開第02/067343号に記載され、いわゆる小分子系のデバイスの例は、米国特許第4,539,507号明細書に記載されている。典型的なOLEDデバイスは2層の有機材料を備え、その一方は、発光ポリマー(LEP)、オリゴマー、または発光低分子量材料のような発光材料の層であり、他方は、ポリチオフェン誘導体またはポリアニリン誘導体のような正孔輸送材料の層である。
しかしながら、改良された画素駆動回路の必要性が存在する。
図1cは、電圧プログラム型OLEDアクティブマトリクス画素回路150の例を示す図である。回路150はディスプレイの各画素に設けられ、Vdd152、接地154、行選択124、および列データ126の各母線が、各画素を相互に接続するように設けられる。このように、各画素は電源接続および接地接続を有し、画素の各行は共通の行選択線124を有し、画素の各列は共通のデータ線126を有する。
B――選択スイッチが有効にされ、基準データ電圧(VHIGH)がフローティングゲートTFT302の入力端子の1つに印加されて(V1=VHIGH)、フローティングゲートTFT302に電流が流れないようにされる(|VFGS|<|Vt|)。VDDはHIGHである。
C――AZがLOW、T3が有効にされる。駆動TFT(T2)の入力V2がドレインに接続されて、T2 302がダイオード接続される。入力V1はまだVHIGHである(V1=VHIGH)。電流がT2を流れ始めて、Vgs/Vdsが増加する。キャパシタC1、C2、およびCgsの間で電荷が再分布する。
D――VDDおよびV1が(Vdataの変化により駆動されて)ΔVだけ低くなる。VD(T2)がLOWになって、OLED301に逆バイアスがかかる。T2を通る電流が向きを変え、有効にされたT3を通ってC2へと流れ込み、容量C2を充電する。電圧V2がHIGHになり、TFT302のフローティングゲートが閾電圧に達するとトランジスタ302のスイッチがオフになる(そしてVtがCgsに記録される)。
E――AZがHIGHになり、T3がオフになり、V2の接続が切れる。
F――VDDおよびV1が(有効にされたT1によって)再びHIGHになり、その結果OLEDが順バイアス状態になる。
G――T2上にプログラムされたデータが、閾電圧Vtでオフセットされる。
Claims (18)
- 複数のアクティブマトリクス画素を有するアクティブマトリクス光電子デバイスであって、前記画素のそれぞれは、前記画素を駆動する薄膜トランジスタ(TFT)を備える画素回路を含み、前記TFTは、フローティングゲートをもつTFTで構成され、フローティングゲートをもつ前記TFTは、前記TFTのゲートへの1つ以上の接続をもつTFTで構成され、前記ゲート接続は、前記TFTの前記ゲートへ容量的にのみ結合された接続で構成され、前記フローティングゲートは、付随するフローティングゲート容量を有し、前記フローティングゲート容量は画素値を蓄える画素キャパシタとして機能するアクティブマトリクス光電子デバイス。
- 前記容量的に結合されたゲート接続は、2つの極板をもつゲート接続キャパシタを備え、前記TFTは、ソース・ドレイン金属層を備え、前記TFTの前記ゲートへの前記容量的に結合された接続は、前記ソース・ドレイン金属層にパターン形成された接続を備え、前記ソース・ドレイン金属層にパターン形成された前記接続は、前記ゲート接続キャパシタの前記極板の一方を備え、前記TFTは、ゲート金属層をさらに備え、前記ゲート金属層は、前記ゲート接続キャパシタの前記極板の第2を備える請求項1に記載のアクティブマトリクス光電子デバイス。
- 前記フローティングゲートは、前記TFTと一体化される請求項1に記載のアクティブマトリクス光電子デバイス。
- 前記デバイスは、有機発光ダイオード(OLED)ディスプレイを備え、前記画素回路は、前記フローティングゲートTFTによって駆動されるOLEDを含む請求項1ないし3のいずれかに記載のアクティブマトリクス光電子デバイス。
- 前記画素回路は、電圧プログラム型画素回路で構成され、前記フローティングゲートTFTは、第1のフローティングゲート接続と第2のフローティングゲート接続を有し、前記電圧プログラム型画素回路は、前記第1のフローティングゲート接続に付随するフローティングゲート容量に前記TFTの閾オフセット電圧値を蓄え、前記第2のフローティン
グゲート接続に付随するフローティングゲート容量に前記画素のプログラミング電圧を蓄える請求項4に記載のアクティブマトリクス光電子デバイス。 - 前記画素回路は、前記閾オフセット電圧値と前記プログラミング電圧とを前記画素キャパシタに提供する動作が、前記フローティングゲートと前記TFTのソース端子またはドレイン端子との間の固有のデバイス容量にプログラミング電圧を蓄えるように構成される請求項5に記載のアクティブマトリクス光電子デバイス。
- 前記画素回路は、前記TFTの前記第2のフローティングゲート接続に結合されたフォトダイオードを含む請求項5または6に記載のアクティブマトリクス光電子デバイス。
- 前記画素回路を制御する制御回路をさらに備え、前記制御回路は、前記OLEDがオフに制御され、前記フローティングゲートキャパシタに前記閾オフセット電圧値を蓄える第1のサイクルと、前記フローティングゲートキャパシタに蓄えられたプログラミング電圧で前記OLEDの明るさが設定される第2のサイクルとの2つのサイクルを有する請求項5ないし7のいずれか1項に記載のアクティブマトリクス光電子デバイス。
- 前記画素回路は、電流プログラム型画素回路で構成され、前記TFTは、第1のフローティングゲート接続と、第2のフローティングゲート接続との2つのフローティングゲート接続を有し、前記電流プログラム型画素回路は、前記第1のフローティングゲート接続が選択トランジスタを介してバイアス線に接続される請求項4に記載のアクティブマトリクス光電子デバイス。
- 前記第1のフローティングゲート接続は、前記フローティングゲートTFTのドレイン接続に結合される請求項9に記載のアクティブマトリクス光電子デバイス。
- 前記第1のフローティングゲート接続は、前記画素回路がプログラミング回路によってプログラミングのために選択され得るようにする少なくとも1つの選択TFTを介して、前記TFTの前記ドレイン接続に結合される請求項10に記載のアクティブマトリクス光電子デバイス。
- 前記TFTは、第1のフローティングゲート接続と、第2のフローティングゲート接続との2つのフローティングゲート接続を有し、前記画素回路は、前記第2のフローティングゲート接続とフローティングゲートTFTのドレイン接続との間に結合された少なくとも1つの選択TFTを含む請求項4に記載のアクティブマトリクス光電子デバイス。
- 前記画素回路は、前記プログラミング電流を前記画素回路へ選択的に提供するために、前記第2のフローティングゲート接続と電流データ線との間に結合された少なくとも1つの選択TFTを含む請求項9ないし12のいずれか1項に記載のアクティブマトリクス光電子デバイス。
- 前記画素回路のプログラミング時に前記OLEDの照明を無効にするための、前記フローティングゲートTFTと前記OLEDとの間に結合された無効化TFTをさらに備える請求項9ないし13のいずれか1項に記載のアクティブマトリクス光電子デバイス。
- 前記フローティングゲートTFTは、2つのフローティングゲート接続を有し、前記画素回路は、前記フローティングゲートTFTの有効な閾電圧制御のために入力端子の一方
を用いるように構成される請求項1ないし14のいずれかに記載のアクティブマトリクス光電子デバイス。 - 前記画素回路は、前記フローティングゲート接続の他方を用いて前記アクティブマトリクス画素のプログラミングを有効にするように構成される請求項15に記載のアクティブマトリクス光電子デバイス。
- 有機エレクトロルミネッセンスディスプレイのアクティブマトリクス画素回路を駆動する方法であって、前記画素回路は、前記画素を駆動する薄膜トランジスタ(TFT)を備え、前記TFTは、フローティングゲートをもつTFTで構成され、フローティングゲートをもつ前記TFTは、前記TFTのゲートへの1つ以上の接続をもつTFTで構成され、前記フローティングゲートは、付随するフローティングゲート・ソース間容量を有する方法において、前記画素回路をプログラムして前記フローティングゲート・ソース間キャパシタに電圧を蓄えることを含み、前記蓄えられた電圧が、前記有機エレクトロルミネッセンス表示素子の明るさを定める方法。
- 前記フローティングゲートTFTは、2つのフローティングゲート接続を有し、前記方法は、前記フローティングゲート接続の第1を用いて前記有機エレクトロルミネッセンス表示画素の前記明るさをプログラムし、前記フローティングゲート接続の第2を用いて前記駆動TFTの閾電圧を変えることを含む請求項17に記載の方法。
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JP2007034006A (ja) * | 2005-07-28 | 2007-02-08 | Victor Co Of Japan Ltd | 有機エレクトロルミネセンス表示装置 |
GB2430069A (en) * | 2005-09-12 | 2007-03-14 | Cambridge Display Tech Ltd | Active matrix display drive control systems |
JP2008058446A (ja) * | 2006-08-30 | 2008-03-13 | Sharp Corp | アクティブマトリクス型表示装置 |
KR100873705B1 (ko) * | 2007-06-22 | 2008-12-12 | 삼성모바일디스플레이주식회사 | 유기전계발광표시장치 및 그의 제조방법 |
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2007
- 2007-11-02 GB GBGB0721567.6A patent/GB0721567D0/en not_active Ceased
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2008
- 2008-10-29 JP JP2010531588A patent/JP5444238B2/ja not_active Expired - Fee Related
- 2008-10-29 GB GB1007074.6A patent/GB2466749B/en not_active Expired - Fee Related
- 2008-10-29 US US12/740,541 patent/US8314756B2/en not_active Expired - Fee Related
- 2008-10-29 WO PCT/GB2008/051007 patent/WO2009056877A1/en active Application Filing
- 2008-10-29 KR KR1020107009672A patent/KR20100077003A/ko active IP Right Grant
- 2008-10-29 DE DE112008002931T patent/DE112008002931T5/de not_active Withdrawn
- 2008-10-29 CN CN2008801216970A patent/CN101903936B/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
TWI467542B (zh) | 2015-01-01 |
GB0721567D0 (en) | 2007-12-12 |
GB201007074D0 (en) | 2010-06-09 |
GB2466749A (en) | 2010-07-07 |
GB0723859D0 (en) | 2008-01-16 |
WO2009056877A1 (en) | 2009-05-07 |
US20100253710A1 (en) | 2010-10-07 |
US8314756B2 (en) | 2012-11-20 |
CN101903936B (zh) | 2013-09-11 |
KR20100077003A (ko) | 2010-07-06 |
DE112008002931T5 (de) | 2010-12-02 |
TW200926112A (en) | 2009-06-16 |
GB2466749B (en) | 2013-05-08 |
CN101903936A (zh) | 2010-12-01 |
JP2011507005A (ja) | 2011-03-03 |
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