JP5380154B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5380154B2 JP5380154B2 JP2009122709A JP2009122709A JP5380154B2 JP 5380154 B2 JP5380154 B2 JP 5380154B2 JP 2009122709 A JP2009122709 A JP 2009122709A JP 2009122709 A JP2009122709 A JP 2009122709A JP 5380154 B2 JP5380154 B2 JP 5380154B2
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- Prior art keywords
- insulator
- layer
- integrated circuit
- semiconductor
- semiconductor integrated
- Prior art date
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本実施の形態では、より信頼性の高い半導体装置、及び歩留まりよい半導体装置の作製方法を、図1乃至図3を用いて詳細に説明する。
本実施の形態では、上記実施の形態と異なる半導体装置の他の例を図14〜図16を用いて説明する。以下に説明する本実施の形態の構成において、実施の形態1と同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。
本実施の形態では、上記実施の形態と異なる半導体装置の他の例について、図17を用いて説明する。以下に説明する本実施の形態の構成において、実施の形態1と同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。
本実施の形態では、上記実施の形態と異なる半導体装置の作製方法について図面を参照して説明する。
本実施の形態では、メモリを有する半導体装置及びその作製方法の一例に関して図6〜図8を用いて説明する。
本実施の形態では、半導体装置の一例として、マイクロプロセッサ及び非接触でデータの送受信を行うことのできる演算機能を備えた半導体装置の一例について説明する。
本実施の形態では、上記実施の形態で示した半導体装置の使用形態の一例について説明する。具体的には、非接触でデータの入出力が可能である半導体装置の適用例に関して、図面を用いて以下に説明する。非接触でデータの入出力が可能である半導体装置は利用の形態によって、RFIDタグ、IDタグ、ICタグ、RFタグ、無線タグ、電子タグまたは無線チップとも呼ばれる。
本実施の形態では、上記実施の形態を用いて形成された非接触でデータの入出力が可能である半導体装置の適用例に関して図面を参照して以下に説明する。
上記実施の形態を用いることにより、プロセッサ回路を有するチップとして機能する半導体装置(RFIDタグ、IDタグ、ICタグ、RFタグ、無線タグ、電子タグまたは無線チップとも呼ばれる)を形成することができる。このような半導体装置の用途は広範にわたり、非接触で対象物の履歴等の情報を明確にし、生産・管理等に役立てる商品であればどのようなものにも適用することができる。例えば、紙幣、硬貨、有価証券類、証書類、無記名債券類、包装用容器類、書籍類、記録媒体、身の回り品、乗物類、食品類、衣類、保健用品類、生活用品類、薬品類及び電子機器等に設けて使用することができる。これらの例に関して図9を用いて説明する。
本実施の形態では、上記実施の形態で示した半導体装置の実装例を、図18を用いて説明する。
101 アンテナ
102 絶縁体
103 絶縁体
104 接着層
105 無機絶縁層
110 基板
111 剥離層
112 絶縁体
113 絶縁体
114 接着層
140 導電性遮蔽体
150 繊維体
151 有機樹脂
160 繊維体
161 有機樹脂
190 チップ
191 チップ
193 チップ
194 チップ
195 チップ
196 チップ
197 チップ
200 基板
201 剥離層
202 絶縁膜
206 チャネル形成領域
207 ゲート絶縁層
208 ゲート電極層
210 トランジスタ
211 トランジスタ
212 絶縁膜
213 絶縁膜
214 絶縁層
226 チャネル形成領域
227 ゲート絶縁層
228 ゲート電極層
250 半導体集積回路
252 絶縁体
254 無機絶縁層
262 絶縁体
263 導電層
270 繊維体
271 有機樹脂
280 繊維体
281 有機樹脂
300 基板
301 剥離層
302 絶縁膜
303 半導体層
304 半導体層
305 半導体層
306 半導体層
308 ゲート絶縁層
309 ゲート絶縁層
310 絶縁膜
311 電荷蓄積層
312 ゲート電極層
313 ゲート電極層
315 制御ゲート電極層
316 ゲート電極層
317 ゲート電極層
318 ゲート電極層
319 制御ゲート電極層
320 不純物元素
321 マスク
323 チャネル形成領域
324 不純物元素
325 マスク
329 チャネル形成領域
330 チャネル形成領域
331 チャネル形成領域
350 半導体集積回路
367 絶縁膜
368 絶縁膜
373 薄膜トランジスタ
374 薄膜トランジスタ
375 メモリ素子
376 薄膜トランジスタ
380 導電層
381 無機絶縁層
382 絶縁体
383 繊維体
384 有機樹脂
385 絶縁体
386 繊維体
387 有機樹脂
388 絶縁体
389 接着層
390 絶縁層
391 絶縁体
395 絶縁体
400 半導体集積回路チップ
405 アンテナ
406 支持基板
407 破線
408 給電点
410 絶縁層
420 半導体装置
421 質問器
422 アンテナ
423 半導体集積回路
424 アンテナ
500 マイクロプロセッサ
501 演算回路
502 演算回路制御部
503 命令解析部
504 制御部
505 タイミング制御部
506 レジスタ
507 レジスタ制御部
508 バスインターフェース
509 専用メモリ
510 メモリインターフェース
511 RFCPU
512 アナログ回路部
513 デジタル回路部
514 共振回路
515 整流回路
516 定電圧回路
517 リセット回路
518 発振回路
519 復調回路
520 変調回路
521 RFインターフェース
522 制御レジスタ
523 クロックコントローラ
524 インターフェース
525 中央処理ユニット
526 ランダムアクセスメモリ
527 専用メモリ
528 アンテナ
529 容量部
530 電源管理回路
600 半導体集積回路チップ
601 可撓性基板
602 可撓性基板
603 可撓性基板
800 半導体装置
810 高周波回路
820 電源回路
830 リセット回路
840 クロック発生回路
850 データ復調回路
860 データ変調回路
870 制御回路
880 記憶回路
890 アンテナ
910 コード抽出回路
920 コード判定回路
930 CRC判定回路
940 出力ユニット回路
140a 導電性遮蔽体
140b 導電性遮蔽体
141a 導電体
141b 導電体
203a 不純物領域
204a ドレイン領域
209a 絶縁層
210a 配線層
223a 不純物領域
224a ドレイン領域
229a 絶縁層
230a 配線層
260a 導電性遮蔽体
260b 導電性遮蔽体
314a ゲート電極層
3200 通信装置
3210 表示部
3220 品物
322a p型不純物領域
322b p型不純物領域
3230 半導体装置
3240 通信装置
3250 半導体装置
3260 商品
326a n型不純物領域
362a n型不純物領域
362b n型不純物領域
364a n型不純物領域
364b n型不純物領域
369a 配線層
369b 配線層
370a 配線層
370b 配線層
371a 配線層
371b 配線層
372a 配線層
372b 配線層
395a 導電性遮蔽体
395b 導電性遮蔽体
Claims (2)
- 第1のチタン膜を有し、
前記第1のチタン膜の上方に第1の絶縁体を有し、
前記第1の絶縁体の上方にトランジスタを有し、
前記トランジスタの上方に絶縁膜を有し、
前記絶縁膜の上方にアンテナを有し、
前記アンテナの上方に第2の絶縁体を有し、
前記第2の絶縁体の上方に第2のチタン膜を有し、
前記第1のチタン膜は、前記第2のチタン膜と電気的に接続され、
前記第1のチタン膜の下側の表面はプラズマにより酸化されており、
前記第2のチタン膜の上側の表面はプラズマにより酸化されていることを特徴とする半導体装置。 - 第1のチタン膜を有し、
前記第1のチタン膜の上方に第1の絶縁体を有し、
前記第1の絶縁体の上方にトランジスタを有し、
前記トランジスタの上方に絶縁膜を有し、
前記絶縁膜の上方にアンテナを有し、
前記アンテナの上方に第2の絶縁体を有し、
前記第2の絶縁体の上方に第2のチタン膜を有し、
前記第1の絶縁体及び前記第2の絶縁体を貫通する針状の導電体を有し、
前記第1のチタン膜は、前記針状の導電体を介して、前記第2のチタン膜と電気的に接続され、
前記第1のチタン膜の下側の表面はプラズマにより酸化されており、
前記第2のチタン膜の上側の表面はプラズマにより酸化されていることを特徴とする半導体装置。
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JP (1) | JP5380154B2 (ja) |
KR (1) | KR101549530B1 (ja) |
CN (1) | CN102037556B (ja) |
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2009
- 2009-05-18 WO PCT/JP2009/059467 patent/WO2009142309A1/en active Application Filing
- 2009-05-18 EP EP09750671A patent/EP2297778A1/en not_active Withdrawn
- 2009-05-18 KR KR1020107028399A patent/KR101549530B1/ko active IP Right Grant
- 2009-05-18 CN CN200980118810.4A patent/CN102037556B/zh not_active Expired - Fee Related
- 2009-05-19 US US12/468,284 patent/US8237248B2/en not_active Expired - Fee Related
- 2009-05-21 JP JP2009122709A patent/JP5380154B2/ja not_active Expired - Fee Related
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US20090289341A1 (en) | 2009-11-26 |
EP2297778A1 (en) | 2011-03-23 |
TW201003894A (en) | 2010-01-16 |
JP2010003295A (ja) | 2010-01-07 |
US8237248B2 (en) | 2012-08-07 |
TWI453892B (zh) | 2014-09-21 |
CN102037556A (zh) | 2011-04-27 |
KR101549530B1 (ko) | 2015-09-02 |
WO2009142309A1 (en) | 2009-11-26 |
KR20110031283A (ko) | 2011-03-25 |
CN102037556B (zh) | 2016-02-10 |
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