JP5214587B2 - フラッシュメモリシステムコントロールスキーム - Google Patents
フラッシュメモリシステムコントロールスキーム Download PDFInfo
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- JP5214587B2 JP5214587B2 JP2009501801A JP2009501801A JP5214587B2 JP 5214587 B2 JP5214587 B2 JP 5214587B2 JP 2009501801 A JP2009501801 A JP 2009501801A JP 2009501801 A JP2009501801 A JP 2009501801A JP 5214587 B2 JP5214587 B2 JP 5214587B2
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- flash memory
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- memory device
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- memory devices
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-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/24—Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
フラッシュメモリ装置106、108、110、112は、それぞれプログラム命令Data[0]、Data[1]、Data[2]、Data[3]に応答する。フラッシュメモリ装置は、直列に接続され、プログラム命令が直列に発せされるので、各フラッシュメモリ装置のコアのプログラム動作は、次のフラッシュメモリ装置の動作と重複するが、プログラム命令を受け取る最後のフラッシュメモリ装置は除かれる。
Claims (6)
- 複数のフラッシュメモリ装置を有するフラッシュメモリシステムの高速損耗レベリングのプログラム方法であって、
i) kページを有するデータファイルを受け取り、kページは0よりも大きい整数であり、
ii) z=k/iの天井関数を計算することにより、フラッシュメモリシステムの構成パラメータとkのサイズに対応するプログラムプロファイルを選択し、当該構成パラメータは、jのフラッシュメモリ装置を含み、jのフラッシュメモリ装置の各々はブロックにつきiページを有し、iとjは、0よりも大きい整数であり、
iii) zがjよりも大きいとき、多重ファイル構造を含むプログラムプロファイルに従い、複数のフラッシュメモリ装置の少なくとも2つの各々にkページのデータファイルのkページの少なくとも1つをプログラムするものであり、前記多重ファイル構造は、j*iページのデータファイルのmユニットをjのフラッシュメモリ装置に格納すること、およびzがjより小さいか等しいとき、k−(m*(j*i))ページのデータファイルをjのフラッシュメモリ装置のzのブロックに格納することを含み、ここで、mは0よりも大きい整数である、プログラム方法。 - 前記プログラムするステップは、j*iページのデータファイルをプログラムするためjのフラッシュメモリ装置の各々にプログラム命令を連続的に提供することを含み、各プログラム命令は、kページの少なくとも1つをプログラムするものである、請求項1に記載の方法。
- 前記プログラムするステップは、k−(m*(j*i))ページをプログラムするためzのフラッシュメモリ装置の各々にプログラム命令を連続的に提供することを含み、各プログラム命令は、kページの少なくとも1つをプログラムするものである、請求項2に記載の方法。
- 複数のフラッシュメモリ装置の少なくとも2つは、互いに直列に接続される、請求項1に記載の方法。
- 複数のフラッシュメモリ装置の少なくとも2つの内の第1のフラッシュメモリ装置は、第1の命令に応答して第1のプログラム動作を実行し、複数のフラッシュメモリ装置の少なくとも2つの内の第2のフラッシュメモリ装置は、第1のフラッシュメモリ装置が第1の動作を実行している間に、第2の命令に応答して第2のプログラム動作を開始する、請求項4に記載の方法。
- 前記第2の命令は、第2のフラッシュメモリ装置が第2のプログラム動作を開始する前に、第1のフラッシュメモリ装置を介して第2のフラッシュメモリ装置に渡される、請求項5に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US78808306P | 2006-03-31 | 2006-03-31 | |
US60/788,083 | 2006-03-31 | ||
PCT/CA2007/000501 WO2007112555A1 (en) | 2006-03-31 | 2007-03-29 | Flash memory system control scheme |
Publications (3)
Publication Number | Publication Date |
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JP2009531747A JP2009531747A (ja) | 2009-09-03 |
JP2009531747A5 JP2009531747A5 (ja) | 2011-04-07 |
JP5214587B2 true JP5214587B2 (ja) | 2013-06-19 |
Family
ID=38563033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009501801A Expired - Fee Related JP5214587B2 (ja) | 2006-03-31 | 2007-03-29 | フラッシュメモリシステムコントロールスキーム |
Country Status (10)
Country | Link |
---|---|
US (2) | US7802064B2 (ja) |
EP (2) | EP2002442B1 (ja) |
JP (1) | JP5214587B2 (ja) |
KR (1) | KR101194965B1 (ja) |
CN (2) | CN101410906B (ja) |
AT (1) | ATE488009T1 (ja) |
DE (1) | DE602007010439D1 (ja) |
ES (1) | ES2498096T3 (ja) |
TW (2) | TW201445576A (ja) |
WO (1) | WO2007112555A1 (ja) |
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- 2007-03-29 EP EP07719433A patent/EP2002442B1/en active Active
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CN101410906A (zh) | 2009-04-15 |
ATE488009T1 (de) | 2010-11-15 |
DE602007010439D1 (de) | 2010-12-23 |
TWI456582B (zh) | 2014-10-11 |
EP2242058A2 (en) | 2010-10-20 |
CN101410906B (zh) | 2015-04-29 |
WO2007112555A1 (en) | 2007-10-11 |
US20070233939A1 (en) | 2007-10-04 |
JP2009531747A (ja) | 2009-09-03 |
KR20090017494A (ko) | 2009-02-18 |
ES2498096T3 (es) | 2014-09-24 |
EP2002442B1 (en) | 2010-11-10 |
EP2002442A1 (en) | 2008-12-17 |
TW200805396A (en) | 2008-01-16 |
EP2242058B1 (en) | 2014-07-16 |
CN102063931B (zh) | 2014-07-30 |
US20100325353A1 (en) | 2010-12-23 |
EP2002442A4 (en) | 2009-05-06 |
EP2242058A3 (en) | 2011-05-25 |
CN102063931A (zh) | 2011-05-18 |
US7802064B2 (en) | 2010-09-21 |
KR101194965B1 (ko) | 2012-10-25 |
TW201445576A (zh) | 2014-12-01 |
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