JP4973046B2 - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 110
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000002184 metal Substances 0.000 claims description 122
- 229910052751 metal Inorganic materials 0.000 claims description 117
- 239000013078 crystal Substances 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 33
- 238000004544 sputter deposition Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- 229910000838 Al alloy Inorganic materials 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 7
- 238000007772 electroless plating Methods 0.000 claims description 7
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 223
- 239000011229 interlayer Substances 0.000 description 13
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 230000001590 oxidative effect Effects 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000011888 foil Substances 0.000 description 5
- 229910001092 metal group alloy Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910018104 Ni-P Inorganic materials 0.000 description 2
- 229910018536 Ni—P Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
図1に本発明の一実施形態における半導体装置の部分断面図を示す。図1は、図5中の領域Aの拡大図であり、半導体基板15の表面上に形成されているAl電極19、Ni層20を拡大した図である。また、図1では、図6と同様の構成部に、図6と同一の符号を付している。
(1)第1実施形態では、異種材質層19bとして、TiやW等の金属で構成された金属層を形成する場合を例として説明したが、この代わりに、Alを主成分とするAl酸化膜を形成することもできる。ただし、この場合、Al酸化膜の膜厚を、第1、第2Al金属層19a、19c間の導電性を確保できるように、きわめて薄くする。例えば、膜厚を20〜30nmとする。
4…上側ヒートシンク、5…ヒートシンクブロック、6…半田、
7…封止用樹脂、9…リードフレーム、10…ボンディングワイヤ、
11…P+型基板、12…N−型層、13…P型層、14…N+型層、
15…半導体基板、16…ゲート電極、17…層間絶縁膜、
18…コンタクトホール、19…Al電極、
19a…第1のAl金属層、19b…異種材質層、19c…第2のAl金属層、
20…Niメッキ層。
Claims (7)
- 半導体素子が形成された半導体基板(15)の表面(15a)上に、前記半導体素子と電気的に接続され、AlもしくはAl合金からなるAl金属層(19)およびNi層(20)が順に形成されている半導体チップ(2)と、
前記半導体チップ(2)の前記Ni層(20)上に配置され、半田(6b)を介して、前記Ni層(20)と接合された導体部材(5)とを備え、
前記Al金属層(19)の表面でのAl結晶粒の結晶面方位が主に(111)面となっている半導体装置の製造方法であって、
前記半導体素子が形成された半導体基板(15)を用意し、前記半導体基板(15)の表面(15a)上に、前記半導体素子と電気的に接続された前記Al金属層(19)を形成する工程と、
前記Al金属層(19)上に前記Ni層(20)を無電解めっき法により形成する工程と、
前記半導体基板(15)をチップ化することで、半導体チップ(2)を形成する工程と、
前記半導体チップ(2)、前記半田(6b)および前記導体部材(5)を用意して、前記半田(6b)により、前記導体部材(5)と前記Ni層(20)とを接合する工程とを有する半導体装置の製造方法において、
前記Al金属層(19)を形成する工程は、前記半導体基板(15)の表面(15a)上に、AlもしくはAl合金からなる第1の層(19a)を形成する工程と、
前記第1の層(19a)の表面に、前記Al金属層(19)の導電性を確保しつつ、前記第1の層中のAl結晶の連続性を断ち切るように、前記第1の層とは材質が異なる異種材質層(19b)を形成する工程と、
前記異種材質層(19b)の表面に、前記第1の層(19a)と同一材料からなる第2の層(19c)を形成する工程とを有することを特徴とする半導体装置の製造方法。 - 前記異種材質層(19b)を形成する工程では、主としてAlとは異なる金属で構成される金属層を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記異種材質層(19b)を形成する工程では、前記第1の層(19a)と前記第2の層(19c)との間での導電性を確保できる厚さであって、Alを主成分とする酸化物からなるAl酸化物層を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の層(19a)を形成する工程では、スパッタリング法により、第1の層(19a)を形成し、
前記異種材質層(19b)を形成する工程では、第1の層(19a)の表面に対して、酸素プラズマ処理を施すことにより、前記Al酸化物層を形成し、
前記第2の層(19c)を形成する工程では、スパッタリング法により、前記第2の層(19c)を形成することを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記第1の層(19a)を形成する工程では、スパッタリング法により、第1の層(19a)を形成し、
前記異種材質層(19b)を形成する工程では、前記第1の層(19a)の表面を酸素に触れさせて、前記表面を自然酸化させることにより、前記Al酸化物層を形成し、
前記第2の層(19c)を形成する工程では、スパッタリング法により、前記第2の層(19c)を形成することを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記第2の層(19c)を形成する工程では、前記第1の層(19a)を形成するときの温度よりも低温下で、前記第2の層(19c)を形成することを特徴とする請求項1ないし5のいずれか1つに記載の半導体装置の製造方法。
- 前記第2の層(19c)を形成する工程では、前記第2の層(19c)を、前記第1の層(19a)よりも薄く形成することを特徴とする請求項1ないし6のいずれか1つに記載の半導体装置の製造方法。
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Cited By (2)
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EP3062341A2 (en) | 2015-02-26 | 2016-08-31 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device with an electrode structure comprising an aluminium or aluminium alloy layer with {110} texture, method of manufacturing said semiconductor device and power conversion device comprising said semiconductor device |
US20210225789A1 (en) * | 2017-08-24 | 2021-07-22 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
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WO2010092691A1 (ja) | 2009-02-16 | 2010-08-19 | トヨタ自動車株式会社 | 半導体装置 |
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JP2016162975A (ja) * | 2015-03-04 | 2016-09-05 | 株式会社東芝 | 半導体装置 |
JP2018121050A (ja) * | 2017-01-24 | 2018-08-02 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
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JP7102723B2 (ja) * | 2017-12-19 | 2022-07-20 | 株式会社デンソー | 半導体装置 |
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JPH04315427A (ja) * | 1991-04-15 | 1992-11-06 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JPH05243229A (ja) * | 1992-02-28 | 1993-09-21 | Nec Corp | 半導体集積回路装置 |
JP4083921B2 (ja) * | 1998-05-29 | 2008-04-30 | 株式会社東芝 | 半導体装置の製造方法 |
JP4171355B2 (ja) * | 2003-06-23 | 2008-10-22 | 株式会社デンソー | モールド型パワーデバイス |
JP3767585B2 (ja) * | 2003-07-11 | 2006-04-19 | 株式会社デンソー | 半導体装置 |
JP2005353838A (ja) * | 2004-06-10 | 2005-12-22 | Matsushita Electric Ind Co Ltd | 半導体記憶装置の製造方法 |
JP2006179881A (ja) * | 2004-11-24 | 2006-07-06 | Tosoh Corp | 配線・電極及びスパッタリングターゲット |
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EP3062341A2 (en) | 2015-02-26 | 2016-08-31 | Hitachi Power Semiconductor Device, Ltd. | Semiconductor device with an electrode structure comprising an aluminium or aluminium alloy layer with {110} texture, method of manufacturing said semiconductor device and power conversion device comprising said semiconductor device |
US20210225789A1 (en) * | 2017-08-24 | 2021-07-22 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US11652072B2 (en) * | 2017-08-24 | 2023-05-16 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
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