JP4750766B2 - 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 - Google Patents
不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 Download PDFInfo
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- JP4750766B2 JP4750766B2 JP2007203823A JP2007203823A JP4750766B2 JP 4750766 B2 JP4750766 B2 JP 4750766B2 JP 2007203823 A JP2007203823 A JP 2007203823A JP 2007203823 A JP2007203823 A JP 2007203823A JP 4750766 B2 JP4750766 B2 JP 4750766B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
- G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7202—Allocation control and policies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/16—Flash programming of all the cells in an array, sector or block simultaneously
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
- Non-Volatile Memory (AREA)
Description
図1は、一般的なフラッシュメモリデバイス内部のアーキテクチャを示す。その主要な特徴として、外部コントローラとのインタフェースを行うための入出力(I/O)バス411と制御信号412と、コマンド信号、アドレス信号および状態信号用のレジスタを用いて内部メモリの動作を制御するメモリ制御回路450が含まれる。フラッシュEEPROMセルからなる1以上のアレイ400が含まれ、各アレイは、アレイ自身の行デコーダ(XDEC)401および列デコーダ(YDEC)402、1グループのセンス増幅器およびプログラム制御回路構成(SA/PROG)454とデータレジスタ404を備えている。現在、メモリセルには記憶エレメントとして1以上の導電性フローティングゲートが通常含まれているが、この代わりに別の長時間電子電荷記憶エレメントを使用してもよい。各記憶エレメントについて設定される2つのレベルの電荷を用いてメモリセルアレイを動作させることも可能であり、したがって各エレメント当り1ビットのデータが格納される。上記とは別に、各記憶エレメントと関連して3以上の記憶状態を設定してもよい。その場合、1ビット以上のデータが各エレメントに格納される。
CS−Chip選択 フラッシュメモリインタフェースの起動に使用さ
れる。
RS−READストローブ メモリアレイからのデータ転送にI/Oバスが使
用中であることを示すために使用される。
WS−Writeストローブ メモリアレイへのデータ転送にI/Oバスが使用
中であることを示すために使用される。
AS−Addressストローブ アドレス情報の転送にI/Oバスが使用中である
ことを示す。
AD[7:0]−アドレス このI/Oバスは、コントローラとメモリ/デー
タバス制御450のフラッシュメモリコマンド用
レジスタ、アドレスレジスタおよびデータレジス
タ間でのデータ転送に使用される。
多くの異なるタイプのフラッシュEEPROMが存在するが、これらの各EEPROMには、狭い集積回路の面積に形成される高いパフォーマンスを示すメモリシステムを動作させるために避ける必要があるそれ自身の制限が存在する。上記タイプのEEPROMのなかには、予めプログラムされたページの中へデータの書込みを全く行わないものもあるため、上述したような置換されたデータを含むページ内でのフラグの更新が不可能なものもある。別のタイプのEEPROMのなかには、このようなフラグの書込みが可能なものもあるが、置換されたデータを含むページに書込みを行うことにより使用状態のままになっている同じブロックの他のページ内のデータが妨害を受ける可能性がある。
プログラミング時間の短縮によりパフォーマンスの改善を図るために、目標として、他のペナルティを受けることなく同時にプログラム可能なできるだけ多くの数のセルをプログラムすることが挙げられる。1つの実装構成では、メモリアレイが、図15の複数ユニット80〜83のような実質的に独立しているサブアレイやユニットに分画され、各ユニットは、図に示すように、多数のブロックに分画される。次いで、データページは2以上のユニットに同時にプログラムされる。別の構成では、これらユニットのうちの1以上のユニットが複数のメモリチップからさらに組み合わされる。これら複数のチップは、より高いデータスループットを達成するための(図2に示すような)単一のバスまたは複数の独立バスと接続することも可能である。この拡張として、プログラミング、読出し、消去を一括して行うために、異なるユニットからのブロックをリンクする方法がある。一例を図15に示す。例えば、ユニット80〜83のそれぞれのユニットから得られるブロック85〜88をメタブロックとして一体に動作させることが可能である。上述したメモリの実施形態の場合と同様、メモリアレイの消去可能な最小のグループである各ブロックが複数ページに分画され、1ページにはブロック内で一体にプログラム可能な最小数のセルが含まれる。したがって、図15に示すメタブロックのプログラミング動作には、通常、メタブロックを形成するブロック85〜88の各ブロックの少なくとも1ページの中へデータを同時にプログラムするステップが含まれ、このプログラミングステップは、メタブロックがいっぱいになるか、着信データがすべてプログラムされてしまうまで反復される。他のメタブロックは、各ユニットから1ブロックずつ、アレイユニットからの異なるブロックから形成される。
Claims (6)
- 再プログラム可能な不揮発性電荷記憶エレメント群のアレイが一括消去可能な記憶エレメントのブロック群に組織化され、各ブロック内の記憶エレメントの複数の各ページが1ユニットとしてプログラム可能となっている前記アレイを有するメモリシステムを動作させる方法であって、
ページ内にデータを書き込むステップの中で、ブロック内のページにデータを順次書き込むステップと、
1以上の更新ページ内に更新データを書き込むことによって、1以上のページ内に先に書き込まれていたデータを更新し、先に書き込まれていたデータのページと更新データのページを同じ論理アドレスで特定するステップと、
データを書き込まれたのとは逆の順序でブロック内のページからデータを順次読み出し、データがすでに読み出されているページと同じ論理アドレスを持ついかなるページ内のデータも無視するステップと、
を有する方法。 - 請求項1記載の方法において、
前記更新し、特定するステップは、ブロック内の全てのページよりも少ない数のページ内のデータを更新しながら、同じブロック内の残りの1以上のページ内のデータは更新しないように制限されている方法。 - 請求項2記載の方法において、
前記方法が実行されるメモリシステムは、電荷記憶エレメントとして導電性フローティングゲートを利用する方法。 - 請求項1記載の方法において、
ページ内にデータを書き込むステップの中で、データが書き込まれる個々のページの論理アドレスも個々のページ内に書き込まれる方法。 - 請求項1記載の方法において、
ページ内にデータを書き込むステップの中で、データが3以上の格納状態を持つページの個々の記憶エレメントに書き込まれ、それによって個々の記憶エレメントに2ビット以上のデータを格納する方法。 - 請求項1記載の方法において、
前記方法が実行されるメモリシステムは、電荷記憶エレメントとして導電性フローティングゲートを利用する方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/766,436 | 2001-01-19 | ||
US09/766,436 US6763424B2 (en) | 2001-01-19 | 2001-01-19 | Partial block data programming and reading operations in a non-volatile memory |
Related Parent Applications (1)
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JP2002558275A Division JP4155824B2 (ja) | 2001-01-19 | 2002-01-07 | 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 |
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Publication Number | Publication Date |
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JP2008004117A JP2008004117A (ja) | 2008-01-10 |
JP4750766B2 true JP4750766B2 (ja) | 2011-08-17 |
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JP2002558275A Expired - Fee Related JP4155824B2 (ja) | 2001-01-19 | 2002-01-07 | 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 |
JP2007203823A Expired - Lifetime JP4750766B2 (ja) | 2001-01-19 | 2007-08-06 | 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 |
JP2008075388A Expired - Lifetime JP4768771B2 (ja) | 2001-01-19 | 2008-03-24 | 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 |
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JP2002558275A Expired - Fee Related JP4155824B2 (ja) | 2001-01-19 | 2002-01-07 | 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 |
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JP2008075388A Expired - Lifetime JP4768771B2 (ja) | 2001-01-19 | 2008-03-24 | 不揮発性メモリにおける部分的ブロックデータのプログラミング動作および読出し動作 |
Country Status (11)
Country | Link |
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US (6) | US6763424B2 (ja) |
EP (4) | EP1653323B1 (ja) |
JP (3) | JP4155824B2 (ja) |
KR (2) | KR100944996B1 (ja) |
CN (3) | CN100485642C (ja) |
AT (1) | ATE327556T1 (ja) |
AU (1) | AU2002236723A1 (ja) |
DE (1) | DE60211653T2 (ja) |
ES (1) | ES2262782T3 (ja) |
TW (1) | TWI221217B (ja) |
WO (1) | WO2002058074A2 (ja) |
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