JP4742661B2 - Manufacturing method of solid-state imaging device - Google Patents

Manufacturing method of solid-state imaging device Download PDF

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JP4742661B2
JP4742661B2 JP2005126815A JP2005126815A JP4742661B2 JP 4742661 B2 JP4742661 B2 JP 4742661B2 JP 2005126815 A JP2005126815 A JP 2005126815A JP 2005126815 A JP2005126815 A JP 2005126815A JP 4742661 B2 JP4742661 B2 JP 4742661B2
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diffusion layer
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敦 正垣
秀司 阿部
正典 大橋
圭司 田谷
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本発明は、固体撮像素子の製造方法、特にＣＭＯＳ固体撮像素子の製造方法に関する。 The present invention relates to a method of manufacturing a solid-state imaging device, more particularly to a method of manufacturing a CMOS solid-state imaging device.

固体撮像素子、いわゆるイメージセンサの微細化に対する要求が強まっており、素子の単位画素を構成する電荷蓄積領域すなわちフォトダイオード（Photo Diode；ＰＤ）の有効面積は減少傾向にある。
従来、固体撮像素子の素子間分離には、電荷蓄積領域が形成された基板にトレンチを形成し、このトレンチ内に絶縁材料を埋め込んだいわゆるＳＴＩ（シャロー・トレンチ・アイソレーション）構造が用いられてきたが、基板材料と絶縁材料の熱膨張係数の違いに起因して結晶欠陥が生じやすいことや、電荷蓄積領域の飽和信号量が減少する要因ともなることが指摘されていた（例えば非特許文献１参照）。 There is an increasing demand for miniaturization of solid-state imaging devices, so-called image sensors, and the effective area of a charge storage region constituting a unit pixel of the device, that is, a photodiode (Photo Diode; PD), is decreasing.
Conventionally, a so-called STI (shallow trench isolation) structure in which a trench is formed in a substrate on which a charge accumulation region is formed and an insulating material is embedded in the trench has been used for element separation of a solid-state imaging device. However, it has been pointed out that crystal defects are likely to occur due to the difference in thermal expansion coefficient between the substrate material and the insulating material, and that the saturation signal amount in the charge accumulation region is reduced (for example, non-patent literature). 1).

このため、ＳＴＩに代わる素子間分離構造として、図１１及び図１２に示すような、不純物拡散による拡散層とその上の絶縁膜による素子間分離構造が提案されている。図１１Ｂは、図１１Ａのａ−ａ線に対応した断面構造を、図１２Ｂは図１２Ａのｂ−ｂ線に対応した断面構造を示す。   For this reason, as an element isolation structure that replaces the STI, an element isolation structure using a diffusion layer formed by impurity diffusion and an insulating film thereon as shown in FIGS. 11 and 12 has been proposed. 11B shows a cross-sectional structure corresponding to the aa line in FIG. 11A, and FIG. 12B shows a cross-sectional structure corresponding to the bb line in FIG. 12A.

この素子間分離構造による固体撮像素子１０１は、第１導電型例えばｎ型の半導体基板（図示せず）上に複数の単位画素１０２が配列された構成において、各単位画素１０２が、少なくとも、隣り合う画素との間の素子分離領域を形成する拡散層１０３及び絶縁層１０４と、単位画素１０２の光電変換部すなわちフォトダイオードを構成する電荷蓄積領域１０５と、この電荷蓄積領域１０５をソースとするフローティングディフュージョン（ＦＤ）を構成する転送ゲート１０８及びドレイン部１０９と、電荷蓄積領域１０５上に設けられたアキューミュレーション層１１０と、このアキューミュレーション層１１０及びドレイン部１０９と転送ゲート１０８とを分離絶縁する酸化膜１１１とを有する。
そして、転送ゲート１０８上にゲート電極（図示せず）が形成されることにより、周辺のＭＯＳトランジスタによる駆動、すなわち撮像動作ならびに転送動作が可能な固体撮像素子が構成される。 The solid-state imaging device 101 having the element isolation structure has a configuration in which a plurality of unit pixels 102 are arranged on a first conductivity type, for example, an n-type semiconductor substrate (not shown). A diffusion layer 103 and an insulating layer 104 that form an element isolation region between matching pixels, a charge storage region 105 that constitutes a photoelectric conversion unit of the unit pixel 102, that is, a photodiode, and a floating that uses this charge storage region 105 as a source A transfer gate 108 and a drain portion 109 constituting a diffusion (FD), an accumulation layer 110 provided on the charge storage region 105, and the accumulation layer 110, the drain portion 109 and the transfer gate 108. And an oxide film 111 for isolation and insulation.
Then, by forming a gate electrode (not shown) on the transfer gate 108, a solid-state imaging device capable of driving by peripheral MOS transistors, that is, an imaging operation and a transfer operation is configured.

このような素子間分離構造による固体撮像素子では、実質的な素子分離がイオン注入等によって形成される拡散層１０３でなされるため、分離幅が拡散層１０３だけの幅となり、従来のＳＴＩによる構成に比して単位画素１０２内における電荷蓄積領域１０５の実効面積を広くすることができる。
米本和也著，ＣＱ出版社「ＣＣＤ／ＣＭＯＳイメージセンサの基礎と応用」 In the solid-state imaging device having such an element isolation structure, since substantial element isolation is performed by the diffusion layer 103 formed by ion implantation or the like, the isolation width is only the width of the diffusion layer 103, and the conventional STI configuration is used. The effective area of the charge storage region 105 in the unit pixel 102 can be widened as compared with FIG.
Kazuya Yonemoto, CQ Publisher “Basics and Applications of CCD / CMOS Image Sensors”

この構成による固体撮像素子においては、素子すなわちイメージセンサの光学特性に大きく寄与する電荷蓄積領域１０５を形成するためのｎ型不純物の注入が、先に形成した絶縁膜１０４をマスクに用いたり、この絶縁膜１０４に対応する形状に選定されたマスクを用いて行われるために、電荷蓄積領域１０５の形状及び実効面積は、絶縁膜１０４の内縁によって規定される構造となる。
この注入されたｎ型不純物は、注入後に絶縁膜１０４の下へ向けて僅かに拡散が進むものの、この拡散によるのみでは、拡散層１０３を構成する高濃度のｐ型不純物に全て打ち消されてしまうことから、実質的な電荷蓄積領域の実効面積増大につながり難い。 In the solid-state imaging device having this configuration, the n-type impurity implantation for forming the charge storage region 105 that greatly contributes to the optical characteristics of the device, that is, the image sensor may be performed using the previously formed insulating film 104 as a mask. Since the process is performed using a mask selected to have a shape corresponding to the insulating film 104, the shape and effective area of the charge storage region 105 have a structure defined by the inner edge of the insulating film 104.
Although the implanted n-type impurity diffuses slightly toward the bottom of the insulating film 104 after the implantation, all of the n-type impurity is canceled by the high-concentration p-type impurity constituting the diffusion layer 103 only by this diffusion. For this reason, it is difficult to substantially increase the effective area of the charge storage region.

しかし、絶縁膜１０４は、ゲート電極のオーバーラップ量や素子間の分離能力を確保するための規格すなわちプロセスルールにおける最小寸法幅で形成されており、その幅を縮小することは困難とされている。したがって、この構成による限り、固体撮像素子の微小化のための単位画素の更なる微細化は、電荷蓄積領域１０５による光電変換部すなわちフォトダイオードの面積縮小によらざるを得ない。
ところが、フォトダイオードの面積縮小は、電荷蓄積量の減少や、Ｓ／Ｎ比の悪化を伴い、ダイナミックレンジの減少などのイメージセンサの撮像特性の悪化につながってしまうという問題がある。 However, the insulating film 104 is formed with the minimum dimension width in the standard, that is, the process rule for ensuring the overlap amount of the gate electrodes and the separation capability between elements, and it is difficult to reduce the width. . Therefore, as long as this configuration is used, further miniaturization of the unit pixel for miniaturization of the solid-state imaging device is inevitably caused by reduction of the area of the photoelectric conversion unit, that is, the photodiode by the charge accumulation region 105.
However, the reduction in the area of the photodiode is accompanied by a decrease in the charge storage amount and a deterioration in the S / N ratio, leading to a deterioration in imaging characteristics of the image sensor such as a reduction in dynamic range.

本発明は、これらの諸問題の解決を図り、電荷蓄積領域の実効面積を犠牲にすることなく単位画素の微小化を可能とする固体撮像素子の製造方法を提供することを目的とする。 An object of the present invention is to solve these various problems and to provide a method for manufacturing a solid-state imaging device that enables miniaturization of unit pixels without sacrificing the effective area of the charge storage region.

本発明による固体撮像素子の製造方法は、第１導電型の電荷蓄積領域により画素が構成され、隣り合う前記画素間が、第２導電型の拡散層とその上の絶縁膜で構成された素子分離手段で分離された固体撮像素子を製造する方法であって、所定濃度の第１導電型の第１の不純物拡散層と、前記第１の不純物拡散層の外側に隣接し、前記第１の不純物拡散層よりも低濃度の第１導電型の第２の不純物拡散層とを、基板の同じ深さにそれぞれ形成し、その後、前記第２の不純物拡散層に、第１導電型の不純物を注入して、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行い、同程度の不純物濃度となった、前記第１の不純物拡散層と前記第２の不純物拡散層とにより、前記電荷蓄積領域を構成し、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程の前或いは後に、前記第２導電型の拡散層を、前記第２の不純物拡散層に隣接して形成し、前記電荷蓄積領域を構成した後に、前記第２導電型の拡散層及び前記第２の不純物拡散層の上を前記第１の不純物拡散層と前記第２の不純物拡散層との境界線上まで覆うように前記絶縁膜を形成することを特徴とする。 In the method of manufacturing a solid-state imaging device according to the present invention, a pixel is configured by a first conductivity type charge storage region, and an element between the adjacent pixels is configured by a second conductivity type diffusion layer and an insulating film thereon. A method of manufacturing a solid-state imaging device separated by a separating unit, the first impurity diffusion layer having a first conductivity type having a predetermined concentration, adjacent to the outside of the first impurity diffusion layer, and First impurity type second impurity diffusion layers having a lower concentration than the impurity diffusion layer are formed at the same depth of the substrate, and then the first conductivity type impurities are added to the second impurity diffusion layer. The step of implanting and making the second impurity diffusion layer have the same impurity concentration as the first impurity diffusion layer is performed, and the first impurity diffusion layer and the first impurity concentration having the same impurity concentration are obtained . by the second impurity diffusion layer constitutes the charge accumulation region, the second Pure things diffusion layer before or after the step of said first impurity concentration of the same level as the impurity diffusion layer, the diffusion layer of the second conductivity type, and formed adjacent to said second impurity diffusion layer, After configuring the charge storage region, the second conductivity type diffusion layer and the second impurity diffusion layer are covered up to the boundary line between the first impurity diffusion layer and the second impurity diffusion layer. The insulating film is formed on the substrate .

また、本発明は、前記固体撮像素子の製造方法において、第１導電型の不純物拡散層を形成する工程と、その後、前記第１導電型の不純物拡散層に第２導電型の不純物を注入することにより、前記第２導電型の拡散層と、前記第２導電型の拡散層に隣接する前記第２の不純物拡散層とを形成し、残りの前記第１導電型の不純物拡散層により前記第１の不純物拡散層を形成する工程とを行い、その後、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行うことを特徴とする。
また、本発明は、前記固体撮像素子の製造方法において、第２導電型の不純物領域に、第１導電型の不純物を注入することにより、前記第１の不純物拡散層と前記第２の不純物拡散層とを同時に形成し、その後、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行い、その後、前記第２の不純物拡散層に隣接して、前記第２導電型の拡散層を形成する工程を行うことを特徴とする。
また、本発明は、前記固体撮像素子の製造方法において、さらに、前記第２の不純物拡散層の上方に第２導電型の不純物を注入して、前記第２導電型の拡散層と同程度の不純物濃度を有する拡散層を形成する工程と、その後、前記第１の不純物拡散層の上方に第２導電型の不純物を注入して、第２導電型のアキューミュレーション層を形成する工程とをさらに行うことを特徴とする。 According to the present invention, in the method of manufacturing the solid-state imaging device, a step of forming a first conductivity type impurity diffusion layer, and then a second conductivity type impurity is implanted into the first conductivity type impurity diffusion layer. Thus, the second conductivity type diffusion layer and the second impurity diffusion layer adjacent to the second conductivity type diffusion layer are formed, and the remaining first conductivity type impurity diffusion layer forms the first conductivity type. Forming a first impurity diffusion layer, and then performing a step of setting the second impurity diffusion layer to an impurity concentration comparable to that of the first impurity diffusion layer.
According to the present invention, in the method of manufacturing the solid-state imaging device, the first impurity diffusion layer and the second impurity diffusion are formed by injecting a first conductivity type impurity into the second conductivity type impurity region. And forming the second impurity diffusion layer at the same impurity concentration as the first impurity diffusion layer, and then adjoining the second impurity diffusion layer, The step of forming the diffusion layer of the second conductivity type is performed.
In the method of manufacturing the solid-state imaging device, the present invention further includes implanting a second conductivity type impurity above the second impurity diffusion layer to obtain the same degree as that of the second conductivity type diffusion layer. Forming a diffusion layer having an impurity concentration, and then implanting a second conductivity type impurity above the first impurity diffusion layer to form a second conductivity type accumulation layer; Is further performed.

本発明に係る固体撮像素子の製造方法によれば、所定濃度の第１導電型の第１の不純物拡散層と、前記第１の不純物拡散層の外側に隣接し、前記第１の不純物拡散層よりも低濃度の第１導電型の第２の不純物拡散層とを、基板の同じ深さにそれぞれ形成し、その後、前記第２の不純物拡散層に、第１導電型の不純物を注入して、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行い、同程度の不純物濃度となった、前記第１の不純物拡散層と前記第２の不純物拡散層とにより、前記電荷蓄積領域を構成することから、電荷蓄積領域の有効面積拡大と飽和信号量増大を図ることができる。 According to the method for manufacturing a solid-state imaging device according to the present invention, the first impurity diffusion layer of the first conductivity type having a predetermined concentration, the first impurity diffusion layer adjacent to the outside of the first impurity diffusion layer, and the first impurity diffusion layer. A second impurity diffusion layer of the first conductivity type having a lower concentration than the first impurity diffusion layer is formed at the same depth of the substrate, and then an impurity of the first conductivity type is implanted into the second impurity diffusion layer. The step of setting the second impurity diffusion layer to the same impurity concentration as the first impurity diffusion layer is performed, and the first impurity diffusion layer and the second impurity having the same impurity concentration are obtained. Since the charge storage region is formed by the diffusion layer, the effective area of the charge storage region and the saturation signal amount can be increased.

以下、図面を参照して本発明の実施の形態を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１に、本発明に係る固体撮像素子の一実施の形態の構成を示す。図１Ｂは、図１Ａのｂ´−ｂ´線上に対応した断面構造を示す。
この実施の形態に係る固体撮像素子１、すなわちＣＭＯＳ固体撮像素子は、第１導電型例えばｎ型のシリコン半導体基板（図示せず）上に第２導電型例えばｐ型の半導体ウェル領域が形成され、このｐ型半導体ウェル領域に、複数の単位画素２が、拡散層３及び絶縁膜４による素子分離領域で相互に絶縁されて区画形成されて成る。 FIG. 1 shows a configuration of an embodiment of a solid-state imaging device according to the present invention. FIG. 1B shows a cross-sectional structure corresponding to the line b′-b ′ in FIG. 1A.
In the solid-state imaging device 1 according to this embodiment, that is, a CMOS solid-state imaging device, a second conductivity type, eg, p-type semiconductor well region is formed on a first conductivity type, eg, n-type silicon semiconductor substrate (not shown). In the p-type semiconductor well region, a plurality of unit pixels 2 are partitioned and formed in an element isolation region by the diffusion layer 3 and the insulating film 4.

各単位画素２は、少なくとも、光電変換部すなわちフォトダイオードを構成する電荷蓄積領域７と、この電荷蓄積領域７をソースとするフローティングディフュージョン（ＦＤ）を構成する転送ゲート８及びドレイン部９と、電荷蓄積領域７上に設けられたアキューミュレーション層１０と、このアキューミュレーション層１０及びドレイン部９と転送ゲート８とを分離絶縁する酸化膜１１とを有する。   Each unit pixel 2 includes at least a charge storage region 7 that forms a photoelectric conversion unit, that is, a photodiode, a transfer gate 8 and a drain unit 9 that form a floating diffusion (FD) that uses the charge storage region 7 as a source, It has an accumulation layer 10 provided on the storage region 7, and an oxide film 11 that isolates and insulates the accumulation layer 10 and the drain portion 9 from the transfer gate 8.

光電変換部すなわちフォトダイオードは、ｎ型基板（図示せず）とｐ型半導体ウェル領域とｎ型電荷蓄積領域７とその表面側のアキューミュレーション層１０とからなるＨＡＤ構造に形成されており、アキューミュレーション層１０により、界面準位による暗電流、すなわち撮像における白点の原因が抑制される。
なお、このアキューミュレーション層１０は、例えば５×１０１７ｃｍ−３以上の高濃度のｐ型不純物拡散層で形成される。 The photoelectric conversion unit, that is, the photodiode, is formed in an HAD structure including an n-type substrate (not shown), a p-type semiconductor well region, an n-type charge storage region 7, and an accumulation layer 10 on the surface side thereof. The accumulation layer 10 suppresses the dark current caused by the interface state, that is, the cause of white spots in imaging.
The accumulation layer 10 is formed of a high concentration p-type impurity diffusion layer of, for example, 5 × 10 17 cm −3 or more.

図２は、この固体撮像素子の、素子分離領域近傍の拡大断面図である。
電荷蓄積領域７は、絶縁膜４の内縁より内側に形成される主要部分５のみならず、絶縁膜４下の主要部分５から連続した位置に形成される延長部分６を有して成る。
この延長部分６は、後述するように、主要部分５とは独立に、例えば２回以上の不純物注入によって形成されることから、素子分離を確保しながらも電荷蓄積領域７の有効面積拡大と飽和信号量増大が図られ、かつ延長部分６のｎ型不純物濃度も、主要部分５のｎ型不純物濃度と同程度に調整することが可能とされる。 FIG. 2 is an enlarged cross-sectional view of the solid-state imaging device in the vicinity of the element isolation region.
The charge storage region 7 includes not only a main portion 5 formed inside the inner edge of the insulating film 4 but also an extended portion 6 formed at a position continuous from the main portion 5 below the insulating film 4.
As will be described later, the extended portion 6 is formed by, for example, two or more impurity implantations independently of the main portion 5, so that the effective area of the charge storage region 7 is expanded and saturated while ensuring element isolation. The signal amount can be increased, and the n-type impurity concentration of the extended portion 6 can be adjusted to the same level as the n-type impurity concentration of the main portion 5.

また、この実施の形態においては、拡散層３と同程度のｐ型不純物濃度を有する延長拡散層１２が、電荷蓄積領域７の延長部分６と絶縁層４との間に、拡散層３とアキューミュレーション層１０をつなぐように形成される。すなわち、延長拡散層１２の幅は電荷蓄積領域７の延長部分６による規制を受けることなく、拡散層３の最狭部のみが延長部分６によってその幅を規定される。
この延長拡散層１２は、後述するように、拡散層３とは独立して、例えば２回以上の不純物注入によって形成されることから、延長拡散層１２のｐ型不純物濃度も拡散層３の不純物濃度と同程度に調整することが可能とされる。
なお、拡散層３は、深さ方向に不純物濃度の分布を形成して、例えば深くなるにしたがって段階的に不純物濃度を低くする構成とすることもできる。 In this embodiment, the extension diffusion layer 12 having a p-type impurity concentration comparable to that of the diffusion layer 3 is provided between the extension portion 6 of the charge storage region 7 and the insulating layer 4 and the diffusion layer 3. It is formed so as to connect the cue simulation layers 10. That is, the width of the extended diffusion layer 12 is not restricted by the extended portion 6 of the charge storage region 7, and only the narrowest portion of the diffusion layer 3 is defined by the extended portion 6.
As will be described later, this extended diffusion layer 12 is formed by, for example, two or more impurity implantations independently of the diffusion layer 3, so that the p-type impurity concentration of the extended diffusion layer 12 is also the impurity of the diffusion layer 3. It is possible to adjust to the same level as the concentration.
Note that the diffusion layer 3 may be configured to form an impurity concentration distribution in the depth direction so that the impurity concentration gradually decreases as the depth increases, for example.

絶縁膜４は、電荷蓄積領域７とアキューミュレーション層１０との界面に形成されるｐｎ接合の位置に比して浅い位置に底が存するように形成されることから、熱ストレスに起因した結晶欠陥の発生を回避でき、更に絶縁膜４上にゲート電極や配線等が乗り上げて形成された場合にも、絶縁膜４直下に空乏化や反転層による寄生チャネルの発生を抑制することができる。
また、絶縁膜４を薄くした場合にも、絶縁膜４直下の拡散層３及び延長拡散層１２のｐ型不純物濃度を高くすることによって、絶縁膜４直下の寄生チャネルの発生を抑止できることから、絶縁膜の厚さは少なくとも１ｎｍ〜１０００ｎｍの間で選定することができる。 Since the insulating film 4 is formed so that the bottom exists at a shallower position than the position of the pn junction formed at the interface between the charge storage region 7 and the accumulation layer 10, the insulating film 4 is caused by thermal stress. Generation of crystal defects can be avoided, and even when a gate electrode, wiring, or the like is formed on the insulating film 4, depletion or generation of a parasitic channel due to an inversion layer can be suppressed immediately below the insulating film 4. .
Further, even when the insulating film 4 is thinned, by increasing the p-type impurity concentration of the diffusion layer 3 and the extension diffusion layer 12 immediately below the insulating film 4, generation of a parasitic channel immediately below the insulating film 4 can be suppressed. The thickness of the insulating film can be selected between at least 1 nm and 1000 nm.

続いて、図３〜図１０を用いて、本発明に係る固体撮像素子の製造方法の第１及び第２の実施の形態を説明する。   Next, first and second embodiments of the method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS.

本発明に係る固体撮像素子の製造方法の第１の実施の形態を、図３〜図６を参照して説明する。この実施の形態では、素子分離領域を隔てて単位画素とトランジスタ領域とが隣り合う場合の製造方法について説明する。   A first embodiment of a method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this embodiment, a manufacturing method in the case where a unit pixel and a transistor region are adjacent to each other with an element isolation region therebetween will be described.

まず、図３Ａに示すように、第１導電型例えばｎ型のシリコン基板３１に第２導電型例えばｐ型の半導体ウェル領域３２を形成したシリコン基体を用意し、このシリコン基体表面にシリコン酸化膜１１を形成し、その上にハードマスクとなるシリコン窒化膜３４を形成した後、例えばレジストマスク（図示せず）を介してフォトダイオードとなる領域にｎ型電荷蓄積領域３３をイオン注入により、例えばｎ型不純物濃度をドーズ量１×１０１２ｃｍ−３程度イオン注入して形成する。 First, as shown in FIG. 3A, a silicon substrate in which a second conductivity type, eg, p-type semiconductor well region 32 is formed on a first conductivity type, eg, n type silicon substrate 31, is prepared, and a silicon oxide film is formed on the surface of the silicon substrate. 11 and a silicon nitride film 34 serving as a hard mask is formed thereon, and then an n-type charge storage region 33 is ion-implanted into a region serving as a photodiode through a resist mask (not shown), for example. An n-type impurity concentration is formed by ion implantation with a dose of about 1 × 10 12 cm −3 .

なお、ｎ型不純物としては、熱処理過程での拡散抑制を考慮して砒素（Ａｓ）を用いることもできるし、燐（Ｐ）を用いても良い。また、電荷蓄積領域３３の形成に際し、フォトダイオードと隣接するところは、後の工程でｐ型不純物で打ち返して素子分離領域を間に形成することができることから、本実施形態におけるように、隣り合う画素については連続して形成することができる。   As the n-type impurity, arsenic (As) can be used in consideration of diffusion suppression in the heat treatment process, or phosphorus (P) can be used. Further, when the charge accumulation region 33 is formed, the portion adjacent to the photodiode can be backed up with p-type impurities in a later step to form an element isolation region therebetween. Pixels can be formed continuously.

次に、図３Ｂに示すように、素子分離領域を形成すべき部分、すなわち隣り合う画素のフォトダイオード間の部分、及び隣り合う画素のフォトダイオードとドレイン間の部分のシリコン窒化膜３４を選択的にエッチング除去し、続いて下層のシリコン酸化膜１１を選択的にエッチング除去して、開口を形成する。   Next, as shown in FIG. 3B, the silicon nitride film 34 in the portion where the element isolation region is to be formed, that is, the portion between the photodiodes of the adjacent pixels and the portion between the photodiode and the drain of the adjacent pixels are selectively formed. Then, the lower silicon oxide film 11 is selectively removed by etching to form an opening.

次に、図４Ｃに示すように、シリコン窒化膜３４及びシリコン酸化膜１１をマスクとして浅いエッチング処理で開口内に露出したシリコン基体表面に浅い溝を掘り、ｐ型不純物をイオン注入して溝の底面に最終的に素子分離領域を構成する拡散層３を形成し、この拡散層３上に、ここで形成した拡散層３の幅より細い開口を残してレジスト３５を形成する。なお、ここでのイオン注入は、例えばボロン（Ｂ）をドーズ量２×１０１２ｃｍ−３〜ドーズ量１×１０１４ｃｍ−３程度、打ち込みエネルギー数ｋｅＶ〜５０ｋｅＶ程度で行う。 Next, as shown in FIG. 4C, using the silicon nitride film 34 and the silicon oxide film 11 as a mask, a shallow groove is dug in the surface of the silicon substrate exposed in the opening by a shallow etching process, and p-type impurities are ion-implanted to form the groove. A diffusion layer 3 that finally forms an element isolation region is formed on the bottom surface, and a resist 35 is formed on the diffusion layer 3 leaving an opening narrower than the width of the diffusion layer 3 formed here. Here, the ion implantation is performed, for example, with boron (B) at a dose of about 2 × 10 12 cm −3 to a dose of about 1 × 10 14 cm −3 and an implantation energy of about keV to about 50 keV.

次に、図４Ｄに示すように、先に形成したレジスト３５の開口内に、つまり既に形成された拡散層３の幅より細い幅で、拡散層３の深さを拡大するイオン注入を行った後、ここでイオン注入した位置の上部にレジスト３６を形成する。なお、ここでのイオン注入は、深さ方向に数回に分けて行い、深さ方向に不純物濃度の分布を形成して、例えば深くなるにしたがって段階的に不純物濃度を低くなるように構成とすることもできる。   Next, as shown in FIG. 4D, ion implantation for expanding the depth of the diffusion layer 3 was performed in the opening of the resist 35 formed earlier, that is, with a width narrower than the width of the diffusion layer 3 already formed. Thereafter, a resist 36 is formed above the position where ions are implanted. Here, the ion implantation is performed several times in the depth direction, and an impurity concentration distribution is formed in the depth direction so that, for example, the impurity concentration gradually decreases as the depth increases. You can also

次に、図５Ｅに示すように、先の工程で形成した拡散層３によって素子間分離がなされて形成された電荷蓄積領域主要部分５の両端に位置する、ｎ型不純物濃度の低下した部分に対して、レジスト３６をマスクとしてｎ型不純物の２回目の注入を行って、最終的に得る固体撮像素子の絶縁膜４が形成される領域の下に、主要部分５と同程度の不純物濃度を有する延長部分６を、主要部分５の形成とは独立に形成して電荷蓄積領域７を完成させる。   Next, as shown in FIG. 5E, the n-type impurity concentration reduced portions located at both ends of the charge storage region main portion 5 formed by element isolation by the diffusion layer 3 formed in the previous step are formed. On the other hand, the second implantation of the n-type impurity is performed using the resist 36 as a mask, and an impurity concentration comparable to that of the main portion 5 is formed under the region where the insulating film 4 of the finally obtained solid-state imaging device is formed. The extended portion 6 is formed independently of the formation of the main portion 5 to complete the charge storage region 7.

次に、図５Ｆに示すように、延長部分６の形成におけるレジストを引き続きマスクとして用いて、先に行ったｎ型不純物の２回目の注入によってｐ型不純物の濃度が低下した拡散層３の表面部分３７に対してｐ型不純物の２回目の注入を行って、電荷蓄積領域７の延長部分６と最終的に得る固体撮像素子の絶縁膜４の形成位置との間に、拡散層３と同程度のｐ型不純物濃度を有する延長拡散層１２を形成し、その後レジストを除去する。   Next, as shown in FIG. 5F, the surface of the diffusion layer 3 in which the concentration of the p-type impurity is lowered by the second implantation of the n-type impurity previously performed using the resist in the formation of the extended portion 6 as a mask. The second implantation of the p-type impurity is performed on the portion 37, and the same as the diffusion layer 3 between the extended portion 6 of the charge storage region 7 and the position where the insulating film 4 of the solid-state imaging device finally obtained is formed. An extended diffusion layer 12 having a p-type impurity concentration of about a degree is formed, and then the resist is removed.

次に、図６に示すように、拡散層３及び延長拡散層１２の上面に絶縁層４を被着形成し、シリコン窒化膜３４表面の高さまで例えばＣＭＰ（化学機械研磨）法により平坦化研磨を行った後、シリコン窒化膜３４を除去し、以降、通常の工程により、トランジスタのドレイン領域９とアキューミュレーション層１０を形成して前述したＨＡＤ構造のフォトダイオードを形成する。
その後、図示しないが、ゲート絶縁膜及びゲート電極を形成して、固体撮像素子の駆動に必要なＭＯＳトランジスタを形成することにより、目的のＣＭＯＳ固体撮像素子を得る。 Next, as shown in FIG. 6, the insulating layer 4 is deposited on the upper surfaces of the diffusion layer 3 and the extended diffusion layer 12, and planarized and polished by, for example, CMP (Chemical Mechanical Polishing) to the height of the surface of the silicon nitride film 34. Thereafter, the silicon nitride film 34 is removed, and thereafter, the drain region 9 and the accumulation layer 10 of the transistor are formed by a normal process to form the above-mentioned photodiode with the HAD structure.
Thereafter, although not shown, a gate insulating film and a gate electrode are formed to form a MOS transistor necessary for driving the solid-state imaging device, thereby obtaining a target CMOS solid-state imaging device.

続いて、本発明に係る固体撮像素子の製造方法の第２の実施の形態を、図７〜図１０を参照して説明する。この実施の形態では、素子分離領域を隔てて単位画素同士のみが隣り合う場合の製造方法について説明する。   Next, a second embodiment of the method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this embodiment, a manufacturing method in the case where only unit pixels are adjacent to each other with an element isolation region therebetween will be described.

まず、図７Ａに示すように、第１導電型例えばｎ型のシリコン基板２１に第２導電型例えばｐ型の半導体ウェル領域２２を形成したシリコン基体を用意し、このシリコン基体表面にシリコン酸化膜１１を形成し、その上にハードマスクとなるシリコン窒化膜２３を形成する。   First, as shown in FIG. 7A, a silicon substrate in which a second conductivity type, eg, p-type semiconductor well region 22 is formed on a first conductivity type, eg, n type silicon substrate 21, is prepared, and a silicon oxide film is formed on the surface of the silicon substrate. 11 is formed, and a silicon nitride film 23 serving as a hard mask is formed thereon.

次に、図７Ｂに示すように、素子分離領域を形成すべき部分、すなわち隣り合う画素のフォトダイオード間の部分、及び隣り合う画素のフォトダイオードとドレイン間の部分のシリコン窒化膜２３を選択的にエッチング除去し、続いて下層のシリコン酸化膜１１を選択的にエッチング除去して、開口を形成する。   Next, as shown in FIG. 7B, the silicon nitride film 23 in the portion where the element isolation region is to be formed, that is, the portion between the photodiodes of the adjacent pixels and the portion between the photodiode and drain of the adjacent pixels are selectively selected. Then, the lower silicon oxide film 11 is selectively removed by etching to form an opening.

次に、図８Ｃに示すように、シリコン窒化膜２３及びシリコン酸化膜１１をマスクとして浅いエッチング処理で開口内に露出したシリコン基体表面に浅い溝を掘り、ｐ型不純物をイオン注入して溝の底面に最終的に素子分離領域を構成する拡散層３を形成し、この拡散層３上にレジスト２４を形成する。なお、ここでのイオン注入は、例えばボロン（Ｂ）をドーズ量２×１０１２ｃｍ−３〜ドーズ量１×１０１４ｃｍ−３程度、打ち込みエネルギー数ｋｅＶ〜５０ｋｅＶ程度で行う。 Next, as shown in FIG. 8C, by using the silicon nitride film 23 and the silicon oxide film 11 as a mask, a shallow groove is dug in the surface of the silicon substrate exposed in the opening by a shallow etching process, and p-type impurities are ion-implanted to form the groove. A diffusion layer 3 that finally forms an element isolation region is formed on the bottom surface, and a resist 24 is formed on the diffusion layer 3. Here, the ion implantation is performed, for example, with boron (B) at a dose of about 2 × 10 12 cm −3 to a dose of about 1 × 10 14 cm −3 and an implantation energy of about keV to about 50 keV.

次に、図８Ｄに示すように、拡散層３の上面にレジスト２４を被着形成し、続いて、図９Ｅに示すように、このレジスト２４をマスクとして、フォトダイオードとなる領域にｎ型電荷蓄積領域の主要部分５を、イオン注入により、例えばｎ型不純物濃度をドーズ量１×１０１２ｃｍ−３程度イオン注入して形成する。 Next, as shown in FIG. 8D, a resist 24 is deposited on the upper surface of the diffusion layer 3, and then, as shown in FIG. 9E, an n-type charge is applied to a region to be a photodiode using the resist 24 as a mask. The main portion 5 of the accumulation region is formed by ion implantation, for example, by ion implantation with an n-type impurity concentration of about 1 × 10 12 cm −3 .

次に、図９Ｆに示すように、先の工程で形成した電荷蓄積領域の主要部分５の両脇に形成された、ｎ型不純物濃度の低い領域２５に対して、レジスト２６をマスクとしてｎ型不純物の２回目の注入を行って、最終的に得る固体撮像素子の絶縁膜４が形成される領域の下に、主要部分５と同程度の不純物濃度を有する延長部分６を、主要部分５の形成とは独立に形成して電荷蓄積領域７を完成させる。   Next, as shown in FIG. 9F, the n-type region 25 having a low n-type impurity concentration is formed on both sides of the main portion 5 of the charge storage region formed in the previous step using the resist 26 as a mask. An extension portion 6 having an impurity concentration similar to that of the main portion 5 is formed below the region where the insulating film 4 of the solid-state imaging device to be finally obtained is formed by performing the second implantation of impurities. The charge accumulation region 7 is completed by forming independently of the formation.

次に、図１０に示すように、延長部分６の形成に用いたレジスト２６を引き続きマスクとして用いて、先に行ったｎ型不純物の２回目の注入によってｐ型不純物の濃度が低下した拡散層３の表面部分２７に対してｐ型不純物の２回目の注入を行って、電荷蓄積領域７の延長部分６と最終的に得る固体撮像素子の絶縁膜４の形成位置との間に、拡散層３と同程度のｐ型不純物濃度を有する延長拡散層１２を形成し、その後レジストを除去し、続いて拡散層３及び延長拡散層１２の上面に絶縁層４を被着形成し、シリコン窒化膜２３を除去し、以降、通常の工程により、トランジスタのドレイン領域９とアキューミュレーション層１０を形成して前述したＨＡＤ構造のフォトダイオードを形成する。
その後、図示しないが、ゲート絶縁膜及びゲート電極を形成して、固体撮像素子の駆動に必要なＭＯＳトランジスタを形成することにより、目的のＣＭＯＳ固体撮像素子を得る。 Next, as shown in FIG. 10, using the resist 26 used for forming the extension portion 6 as a mask, the diffusion layer in which the concentration of the p-type impurity is reduced by the second implantation of the n-type impurity previously performed. P-type impurity is injected into the surface portion 27 for the second time between the extended portion 6 of the charge storage region 7 and the position where the insulating film 4 of the solid-state imaging device finally obtained is formed. The extension diffusion layer 12 having a p-type impurity concentration equivalent to 3 is formed, and then the resist is removed. Then, the insulating layer 4 is deposited on the upper surfaces of the diffusion layer 3 and the extension diffusion layer 12, and the silicon nitride film After that, the drain region 9 of the transistor and the accumulation layer 10 are formed by a normal process to form the above-mentioned photodiode with the HAD structure.
Thereafter, although not shown, a gate insulating film and a gate electrode are formed to form a MOS transistor necessary for driving the solid-state imaging device, thereby obtaining a target CMOS solid-state imaging device.

以上、本発明に係る固体撮像素子及び固体撮像素子の製造方法の実施の形態を説明したが、本発明は、この実施の形態に限られるものではない。   As mentioned above, although embodiment of the manufacturing method of the solid-state image sensor concerning this invention and a solid-state image sensor was described, this invention is not limited to this embodiment.

例えば、本発明による固体撮像素子の製造方法によれば、絶縁膜の幅によらずにフォトダイオードの電荷蓄積領域を設定することが可能になることから、電荷蓄積領域の実効面積を広げる目的に限らず、フォトダイオード周辺で互いに隣り合う素子間の電界強度が弱いところについては拡散層による分離幅を狭め、電界強度が強いところについては拡散層による分離幅を広げるなど、選択的な所望の素子分離パターン形成を目的とした固体撮像素子の製造に適用することもできる。   For example, according to the method for manufacturing a solid-state imaging device according to the present invention, it is possible to set the charge accumulation region of the photodiode regardless of the width of the insulating film, so that the effective area of the charge accumulation region can be increased. Not limited to the desired element, such as narrowing the separation width by the diffusion layer for areas where the electric field strength between adjacent elements is weak around the photodiode, and increasing the separation width by the diffusion layer for areas where the electric field strength is strong. The present invention can also be applied to manufacture of a solid-state imaging device for the purpose of forming a separation pattern.

また、例えば、電荷蓄積領域を構成する延長部分や素子分離領域を構成する延長拡散層を、電荷蓄積領域を構成する主要部分や素子分離領域を構成する拡散層と独立して形成する際に注入する不純物は、必ずしも主要部分や拡散層の形成に用いた不純物と同一物質でなくとも、同じ極性を持つ不純物であれば良いなど、本発明は、種々の変更及び変形をなされ得る。   In addition, for example, it is injected when an extension part constituting the charge storage region and an extension diffusion layer constituting the element isolation region are formed independently from the main part constituting the charge storage region and the diffusion layer constituting the element isolation region. The present invention can be variously modified and modified such that the impurity having the same polarity is not necessarily the same material as the impurity used for forming the main portion and the diffusion layer.

Ａ，Ｂ 本発明に係る固体撮像素子の一例の構成を示す概略上面図及び概略断面図である。A and B are a schematic top view and a schematic cross-sectional view showing a configuration of an example of a solid-state imaging device according to the present invention. 本発明に係る固体撮像素子の一例の構成を示す拡大断面図である。It is an expanded sectional view showing the composition of an example of the solid-state image sensing device concerning the present invention. Ａ，Ｂ 本発明に係る固体撮像素子の製造方法の一例の説明に供する工程図である。A and B are process diagrams for explaining an example of a method for manufacturing a solid-state imaging device according to the present invention. Ｃ，Ｄ 本発明に係る固体撮像素子の製造方法の一例の説明に供する工程図である。C and D are process diagrams for explaining an example of a method for manufacturing a solid-state imaging device according to the present invention. Ｅ，Ｆ 本発明に係る固体撮像素子の製造方法の一例の説明に供する工程図である。E and F are process diagrams for explaining an example of a method for manufacturing a solid-state imaging device according to the present invention. 本発明に係る固体撮像素子の製造方法の一例の説明に供する工程図である。It is process drawing with which it uses for description of an example of the manufacturing method of the solid-state image sensor which concerns on this invention. Ａ，Ｂ 本発明に係る固体撮像素子の製造方法の他の例の説明に供する工程図である。A and B are process diagrams for explaining another example of a method for manufacturing a solid-state imaging device according to the present invention. Ｃ，Ｄ 本発明に係る固体撮像素子の製造方法の他の例の説明に供する工程図である。C, D It is process drawing with which it uses for description of the other example of the manufacturing method of the solid-state image sensor concerning this invention. Ｅ，Ｆ 本発明に係る固体撮像素子の製造方法の他の例の説明に供する工程図である。E, F It is process drawing with which it uses for description of the other example of the manufacturing method of the solid-state image sensor concerning this invention. 本発明に係る固体撮像素子の製造方法の他の例の説明に供する工程図である。It is process drawing for description of the other example of the manufacturing method of the solid-state image sensor which concerns on this invention. Ａ，Ｂ 従来の固体撮像素子の構成を示す概略上面図及び概略断面図である。A and B are a schematic top view and a schematic cross-sectional view showing a configuration of a conventional solid-state imaging device. Ａ，Ｂ 従来の固体撮像素子の構成を示す概略上面図及び概略断面図である。A and B are a schematic top view and a schematic cross-sectional view showing a configuration of a conventional solid-state imaging device.

符号の説明Explanation of symbols

１・・・固体撮像素子、２・・・単位画素、３・・・拡散層、４・・・絶縁膜、５・・・主要部分、６・・・延長部分、７・・・電荷蓄積領域、８・・・転送ゲート、９・・・ドレイン部、１０・・・アキューミュレーション層、１１・・・酸化膜、１２・・・延長拡散層、２１・・・半導体基板、２２・・・半導体ウェル領域、２３・・・ハードマスク、２４・・・レジスト、２５・・・低不純物濃度領域、２６・・・レジスト、２７・・・表面部分、３１・・・半導体基板、３２・・・半導体ウェル領域、３３・・・電荷蓄積領域、３４・・・ハードマスク、３５・・・レジスト、３６・・・レジスト、３７・・・表面部分、１０１・・・固体撮像素子、１０２・・・単位画素、１０３・・・拡散層、１０４・・・絶縁膜、１０５・・・電荷蓄積領域、１０８・・・転送ゲート、１０９・・・ドレイン部、１１０・・・アキューミュレーション層、１１１・・・酸化膜   DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 2 ... Unit pixel, 3 ... Diffusion layer, 4 ... Insulating film, 5 ... Main part, 6 ... Extension part, 7 ... Charge storage area 8 ... Transfer gate, 9 ... Drain portion, 10 ... Accumulation layer, 11 ... Oxide film, 12 ... Extended diffusion layer, 21 ... Semiconductor substrate, 22 ... Semiconductor well region, 23 ... hard mask, 24 ... resist, 25 ... low impurity concentration region, 26 ... resist, 27 ... surface portion, 31 ... semiconductor substrate, 32 ... Semiconductor well region 33: Charge storage region 34 ... Hard mask 35 ... Resist 36 ... Resist 37 ... Surface portion 101 ... Solid-state image sensor 102 ... Unit pixel 103 ... Diffusion layer 104 ... Insulating film 105 ... Load storage area 108 ... transfer gate, 109 ... drain unit, 110 ... accumulation layer, 111 ... oxide film

Claims (4)

第１導電型の電荷蓄積領域により画素が構成され、隣り合う前記画素間が、第２導電型の拡散層とその上の絶縁膜で構成された素子分離手段で分離された固体撮像素子を製造する方法であって、
所定濃度の第１導電型の第１の不純物拡散層と、前記第１の不純物拡散層の外側に隣接し、前記第１の不純物拡散層よりも低濃度の第１導電型の第２の不純物拡散層とを、基板の同じ深さにそれぞれ形成し、
その後、前記第２の不純物拡散層に、第１導電型の不純物を注入して、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行い、
同程度の不純物濃度となった、前記第１の不純物拡散層と前記第２の不純物拡散層とにより、前記電荷蓄積領域を構成し、
前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程の前或いは後に、前記第２導電型の拡散層を、前記第２の不純物拡散層に隣接して形成し、
前記電荷蓄積領域を構成した後に、前記第２導電型の拡散層及び前記第２の不純物拡散層の上を前記第１の不純物拡散層と前記第２の不純物拡散層との境界線上まで覆うように前記絶縁膜を形成する
固体撮像素子の製造方法。 Manufactures a solid-state imaging device in which a pixel is constituted by a charge accumulation region of the first conductivity type, and the adjacent pixels are separated by an element separation means constituted by a diffusion layer of a second conductivity type and an insulating film thereon. A way to
A first impurity diffusion layer of a first conductivity type having a predetermined concentration, and a second impurity of the first conductivity type adjacent to the outside of the first impurity diffusion layer and having a lower concentration than the first impurity diffusion layer. Each of the diffusion layers is formed at the same depth of the substrate,
Thereafter, a step of injecting a first conductivity type impurity into the second impurity diffusion layer to make the second impurity diffusion layer have an impurity concentration comparable to that of the first impurity diffusion layer,
The charge storage region is configured by the first impurity diffusion layer and the second impurity diffusion layer having the same impurity concentration ,
Before or after the step of setting the second impurity diffusion layer to the same impurity concentration as that of the first impurity diffusion layer, the second conductivity type diffusion layer is adjacent to the second impurity diffusion layer. Forming,
After configuring the charge storage region, the second conductivity type diffusion layer and the second impurity diffusion layer are covered up to the boundary line between the first impurity diffusion layer and the second impurity diffusion layer. A method for manufacturing a solid-state imaging device , wherein the insulating film is formed on the substrate. 第１導電型の不純物拡散層を形成する工程と、
その後、前記第１導電型の不純物拡散層に第２導電型の不純物を注入することにより、前記第２導電型の拡散層と、前記第２導電型の拡散層に隣接する前記第２の不純物拡散層とを形成し、残りの前記第１導電型の不純物拡散層により前記第１の不純物拡散層を形成する工程とを行い、
その後、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行う
請求項１に記載の固体撮像素子の製造方法。 Forming a first conductivity type impurity diffusion layer;
Thereafter, by implanting a second conductivity type impurity into the first conductivity type impurity diffusion layer, the second conductivity type diffusion layer and the second impurity adjacent to the second conductivity type diffusion layer. Forming a diffusion layer, and forming the first impurity diffusion layer with the remaining impurity diffusion layers of the first conductivity type,
2. The method for manufacturing a solid-state imaging element according to claim 1, wherein a step of setting the second impurity diffusion layer to an impurity concentration comparable to that of the first impurity diffusion layer is performed. 第２導電型の不純物領域に、第１導電型の不純物を注入することにより、前記第１の不純物拡散層と前記第２の不純物拡散層とを同時に形成し、
その後、前記第２の不純物拡散層を前記第１の不純物拡散層と同程度の不純物濃度とする工程を行い、
その後、前記第２の不純物拡散層に隣接して、前記第２導電型の拡散層を形成する工程を行う
請求項１に記載の固体撮像素子の製造方法。 By implanting a first conductivity type impurity into the second conductivity type impurity region, the first impurity diffusion layer and the second impurity diffusion layer are formed simultaneously;
Thereafter, a step of setting the second impurity diffusion layer to an impurity concentration comparable to that of the first impurity diffusion layer is performed.
2. The method for manufacturing a solid-state imaging element according to claim 1, wherein a step of forming the second conductivity type diffusion layer adjacent to the second impurity diffusion layer is performed. 前記第２の不純物拡散層の上方に第２導電型の不純物を注入して、前記第２導電型の拡散層と同程度の不純物濃度を有する拡散層を形成する工程と、その後、前記第１の不純物拡散層の上方に第２導電型の不純物を注入して、第２導電型のアキューミュレーション層を形成する工程とをさらに行う、請求項１〜請求項３のいずれか１項に記載の固体撮像素子の製造方法。 A step of implanting a second conductivity type impurity above the second impurity diffusion layer to form a diffusion layer having an impurity concentration comparable to that of the second conductivity type diffusion layer; by implanting an impurity of a second conductivity type above the impurity diffusion layer, further performing the step of forming the accumulation layer of the second conductivity type, to any one of claims 1 to 3 The manufacturing method of the solid-state image sensor of description.
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