JP4286634B2 - メモリ故障救済回路 - Google Patents
メモリ故障救済回路 Download PDFInfo
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- JP4286634B2 JP4286634B2 JP2003372027A JP2003372027A JP4286634B2 JP 4286634 B2 JP4286634 B2 JP 4286634B2 JP 2003372027 A JP2003372027 A JP 2003372027A JP 2003372027 A JP2003372027 A JP 2003372027A JP 4286634 B2 JP4286634 B2 JP 4286634B2
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- Prior art keywords
- circuit
- memory
- power supply
- semiconductor integrated
- relief
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-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
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- Semiconductor Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
図1は、本発明の実施の形態1のメモリ故障救済回路の構成を示すブロック図である。図1において、メモリ故障救済回路は、実機能を実現しているロジック回路1と、ロジック回路1が使用するメモリ部2と、メモリ部2の故障の有無を判定する自己診断回路3と、自己診断回路3の判定結果からヒューズ制御等によりメモリ部2の欠陥個所との置き換えを行う冗長回路4と、ロジック回路1が指定するメモリのアドレスと自己診断回路3から出力される判定結果(欠陥箇所を示すアドレス)とを比較する比較器5と、比較器5の比較結果からメモリ部2に欠陥個所がある場合に、ロジック回路1の冗長回路4へのアクセスを可能とするセレクタ6とを備える。
図3は、本発明の実施の形態2のメモリ故障救済回路の構成を示すブロック図である。なお、図1と同一部分には同一符号を付して説明する。図3において、メモリ故障救済回路は、ロジック回路1と、メモリ部2と、冗長回路4と、半導体集積回路の検査結果を保持するフラッシュメモリ9と、ロジック回路1が指定するアドレスとフラッシュメモリ9に記憶されている判定結果とを比較する比較器5と、比較器5の比較結果からメモリ部2に欠陥メモリセルがある場合にロジック回路1の冗長回路4へのアクセスを可能とするセレクタ6とを備える。
2 メモリ部
3 自己診断回路
4 冗長回路
5 比較器
6 セレクタ
7 フラッシュメモリ
10 電源制御回路
Claims (9)
- メモリを有する半導体集積回路のメモリ故障を救済するメモリ故障救済回路であって、
前記メモリを診断し、診断結果を電源制御回路へ出力する自己診断回路からの診断結果に基づいて前記メモリの欠陥個所に置き換えられる冗長回路と比較器とを有する冗長救済回路と、前記半導体集積回路に対する電源とは別系統の、前記冗長救済回路に電源供給する電源ラインとを備え、
前記冗長救済回路に対する電源供給が前記診断結果に基づいて作動する前記電源制御回路により前記半導体集積回路に対する電源供給から独立して制御されるメモリ故障救済回路。 - 前記冗長救済回路は、前記半導体集積回路の検査時の前記メモリの診断結果を保持する保持手段に保持された診断結果に基づいて前記メモリの欠陥個所に置き換えられる冗長回路を有するものである請求項1記載のメモリ故障救済回路。
- 前記冗長救済回路に対する電源が前記半導体集積回路とは異なる電源から供給される請求項1または2記載のメモリ故障救済回路。
- 前記自己診断回路は、電源投入ごとに作動して得られる前記メモリの診断結果を前記電源制御回路へ出力する請求項1または3記載のメモリ故障救済回路。
- 前記メモリの欠陥個所との置き換えをヒューズ制御で行う請求項1から4のいずれか一項記載のメモリ故障救済回路。
- 前記電源制御回路が、前記半導体集積回路の外部にある請求項1から5のいずれか一項記載のメモリ故障救済回路。
- 前記電源制御回路が、前記半導体集積回路の内部にある請求項1から5のいずれか一項記載のメモリ故障救済回路。
- 請求項1記載のメモリ故障救済回路の電源制御方法であって、
前記メモリの診断結果に基づいて前記冗長回路を前記メモリの欠陥箇所に置き換える場合にのみ、前記冗長救済回路に対する電源供給を行うメモリ故障救済回路の電源制御方法。 - 請求項1記載のメモリ故障救済回路の電源配線方法であって、
前記メモリの診断結果に基づいて前記冗長回路を前記メモリの欠陥個所に置き換えない場合、前記冗長救済回路に対する電源供給ラインをトリミングでカットするメモリ故障救済回路の電源配線方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003372027A JP4286634B2 (ja) | 2002-11-20 | 2003-10-31 | メモリ故障救済回路 |
CNB2003101180802A CN100474442C (zh) | 2002-11-20 | 2003-11-20 | 存储器故障消除电路及其电源控制方法 |
US10/716,876 US6967879B2 (en) | 2002-11-20 | 2003-11-20 | Memory trouble relief circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002336566 | 2002-11-20 | ||
JP2003372027A JP4286634B2 (ja) | 2002-11-20 | 2003-10-31 | メモリ故障救済回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004185795A JP2004185795A (ja) | 2004-07-02 |
JP4286634B2 true JP4286634B2 (ja) | 2009-07-01 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003372027A Expired - Fee Related JP4286634B2 (ja) | 2002-11-20 | 2003-10-31 | メモリ故障救済回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6967879B2 (ja) |
JP (1) | JP4286634B2 (ja) |
CN (1) | CN100474442C (ja) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006079418A (ja) | 2004-09-10 | 2006-03-23 | Fujitsu Ltd | 記憶制御装置、制御方法及びプログラム |
JP4917767B2 (ja) * | 2005-07-01 | 2012-04-18 | パナソニック株式会社 | 半導体記憶装置 |
US7411844B2 (en) * | 2005-11-30 | 2008-08-12 | Infineon Technologies Flash Gmbh & Co. Kg | Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit |
DE102005061719B3 (de) | 2005-12-22 | 2007-05-16 | Infineon Technologies Ag | Speichervorrichtung mit Fuse-Speicherelementen |
JP4865360B2 (ja) * | 2006-03-01 | 2012-02-01 | パナソニック株式会社 | 半導体記憶装置 |
JP5322346B2 (ja) * | 2007-06-07 | 2013-10-23 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP5104123B2 (ja) * | 2007-08-17 | 2012-12-19 | 富士通セミコンダクター株式会社 | 半導体メモリ |
US9224496B2 (en) | 2010-08-11 | 2015-12-29 | Shine C. Chung | Circuit and system of aggregated area anti-fuse in CMOS processes |
US8830720B2 (en) | 2010-08-20 | 2014-09-09 | Shine C. Chung | Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices |
US10249379B2 (en) | 2010-08-20 | 2019-04-02 | Attopsemi Technology Co., Ltd | One-time programmable devices having program selector for electrical fuses with extended area |
US9251893B2 (en) | 2010-08-20 | 2016-02-02 | Shine C. Chung | Multiple-bit programmable resistive memory using diode as program selector |
US10923204B2 (en) | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
US9025357B2 (en) | 2010-08-20 | 2015-05-05 | Shine C. Chung | Programmable resistive memory unit with data and reference cells |
US9496033B2 (en) | 2010-08-20 | 2016-11-15 | Attopsemi Technology Co., Ltd | Method and system of programmable resistive devices with read capability using a low supply voltage |
US8488359B2 (en) | 2010-08-20 | 2013-07-16 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices |
US9824768B2 (en) | 2015-03-22 | 2017-11-21 | Attopsemi Technology Co., Ltd | Integrated OTP memory for providing MTP memory |
US9042153B2 (en) | 2010-08-20 | 2015-05-26 | Shine C. Chung | Programmable resistive memory unit with multiple cells to improve yield and reliability |
US8854859B2 (en) | 2010-08-20 | 2014-10-07 | Shine C. Chung | Programmably reversible resistive device cells using CMOS logic processes |
US9818478B2 (en) | 2012-12-07 | 2017-11-14 | Attopsemi Technology Co., Ltd | Programmable resistive device and memory using diode as selector |
US9070437B2 (en) | 2010-08-20 | 2015-06-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink |
US10229746B2 (en) | 2010-08-20 | 2019-03-12 | Attopsemi Technology Co., Ltd | OTP memory with high data security |
US9236141B2 (en) | 2010-08-20 | 2016-01-12 | Shine C. Chung | Circuit and system of using junction diode of MOS as program selector for programmable resistive devices |
US9019742B2 (en) | 2010-08-20 | 2015-04-28 | Shine C. Chung | Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory |
US9711237B2 (en) | 2010-08-20 | 2017-07-18 | Attopsemi Technology Co., Ltd. | Method and structure for reliable electrical fuse programming |
US9431127B2 (en) | 2010-08-20 | 2016-08-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices |
US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
US9460807B2 (en) | 2010-08-20 | 2016-10-04 | Shine C. Chung | One-time programmable memory devices using FinFET technology |
US9019791B2 (en) | 2010-11-03 | 2015-04-28 | Shine C. Chung | Low-pin-count non-volatile memory interface for 3D IC |
US8913449B2 (en) * | 2012-03-11 | 2014-12-16 | Shine C. Chung | System and method of in-system repairs or configurations for memories |
US9076513B2 (en) | 2010-11-03 | 2015-07-07 | Shine C. Chung | Low-pin-count non-volatile memory interface with soft programming capability |
US8988965B2 (en) | 2010-11-03 | 2015-03-24 | Shine C. Chung | Low-pin-count non-volatile memory interface |
CN102544011A (zh) | 2010-12-08 | 2012-07-04 | 庄建祥 | 反熔丝存储器及电子*** |
US10192615B2 (en) | 2011-02-14 | 2019-01-29 | Attopsemi Technology Co., Ltd | One-time programmable devices having a semiconductor fin structure with a divided active region |
US8848423B2 (en) | 2011-02-14 | 2014-09-30 | Shine C. Chung | Circuit and system of using FinFET for building programmable resistive devices |
US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
US9324849B2 (en) | 2011-11-15 | 2016-04-26 | Shine C. Chung | Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC |
US9136261B2 (en) | 2011-11-15 | 2015-09-15 | Shine C. Chung | Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection |
US8912576B2 (en) | 2011-11-15 | 2014-12-16 | Shine C. Chung | Structures and techniques for using semiconductor body to construct bipolar junction transistors |
US8917533B2 (en) | 2012-02-06 | 2014-12-23 | Shine C. Chung | Circuit and system for testing a one-time programmable (OTP) memory |
US9007804B2 (en) | 2012-02-06 | 2015-04-14 | Shine C. Chung | Circuit and system of protective mechanisms for programmable resistive memories |
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US9324447B2 (en) | 2012-11-20 | 2016-04-26 | Shine C. Chung | Circuit and system for concurrently programming multiple bits of OTP memory devices |
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US10726914B2 (en) | 2017-04-14 | 2020-07-28 | Attopsemi Technology Co. Ltd | Programmable resistive memories with low power read operation and novel sensing scheme |
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US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
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JPH10289597A (ja) * | 1997-04-14 | 1998-10-27 | Advantest Corp | メモリ試験装置 |
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JPH11238395A (ja) * | 1998-02-20 | 1999-08-31 | Advantest Corp | メモリ試験装置 |
JP2001035192A (ja) * | 1999-07-19 | 2001-02-09 | Nec Corp | メモリ搭載集積回路およびそのテスト方法 |
JP4230061B2 (ja) * | 1999-07-21 | 2009-02-25 | 株式会社アドバンテスト | 不良救済解析器を搭載したメモリ試験装置 |
JP2001266589A (ja) * | 2000-03-21 | 2001-09-28 | Toshiba Corp | 半導体記憶装置およびそのテスト方法 |
JP2002150789A (ja) * | 2000-11-09 | 2002-05-24 | Hitachi Ltd | 不揮発性半導体記憶装置 |
JP2003068071A (ja) * | 2001-08-30 | 2003-03-07 | Hitachi Ltd | 半導体メモリ |
-
2003
- 2003-10-31 JP JP2003372027A patent/JP4286634B2/ja not_active Expired - Fee Related
- 2003-11-20 US US10/716,876 patent/US6967879B2/en not_active Expired - Fee Related
- 2003-11-20 CN CNB2003101180802A patent/CN100474442C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6967879B2 (en) | 2005-11-22 |
JP2004185795A (ja) | 2004-07-02 |
CN100474442C (zh) | 2009-04-01 |
CN1512510A (zh) | 2004-07-14 |
US20040151022A1 (en) | 2004-08-05 |
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