JP4130621B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4130621B2 JP4130621B2 JP2003371005A JP2003371005A JP4130621B2 JP 4130621 B2 JP4130621 B2 JP 4130621B2 JP 2003371005 A JP2003371005 A JP 2003371005A JP 2003371005 A JP2003371005 A JP 2003371005A JP 4130621 B2 JP4130621 B2 JP 4130621B2
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- conductive film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は、本発明の第1実施形態に係る半導体装置の断面構造を示す図である。図1に示すように、半導体基板1の表面にトランジスタ2が形成される。トランジスタ2は、半導体基板上のゲート絶縁膜(図示せぬ)上に形成されたゲート電極3、半導体基板1の表面でゲート電極3を挟むように形成されたソース/ドレイン拡散層4を有する。ソース/ドレイン拡散層4の表面には、シリサイド5が形成されている。
第2実施形態では、コンタクトホールの一部が第1導電膜13により埋め込まれ、残りが配線層を構成する第2導電膜24と同じ材料により埋め込まれる。
第3実施形態は、第1実施形態の構成に加えて、コンタクトホール12がバリアメタルを介して埋め込まれる。
第4実施形態は、第2実施形態の構成に加え、コンタクトホール12がバリアメタルを介して埋め込まれる。
5…シリサイド、11…層間絶縁膜、12…コンタクトホール、12a…第1領域、12b…第2領域、13…第1導電膜、21…層間絶縁膜、22…配線溝、23…バリアメタル、24…第2導電膜、31…バリアメタル。
Claims (3)
- 半導体基板と、
前記半導体基板上に形成され、且つ前記半導体基板の表面に形成された接続領域を有する能動素子構造と、
前記半導体基板上に形成された絶縁膜と、
前記絶縁膜内に形成され、底部が前記接続領域と接続され、第1領域と前記第1領域上に形成された第2領域とを有する、接続孔と、
前記絶縁膜内に形成され、且つ底部が前記接続孔と接続された、配線溝と、
前記接続孔内の前記第1領域に埋め込まれ、且つCoWまたはNiWを含む合金により構成された、第1導電膜と、
前記配線溝内と前記接続孔の前記第2領域とに配設され、且つ前記第1導電膜に電気的に接続された第2導電膜と、
前記配線溝の内表面と前記第2導電膜との間、前記第2領域の接続孔の側面と前記第2導電膜との間、及び前記第1導電膜上とに形成された第1拡散防止膜と、
前記第1領域の前記接続孔の底面と前記第1導電膜との間、前記第1領域の前記接続孔の側面と前記第1導電膜との間、及び前記第2領域の接続孔の前記側面と前記第1拡散防止膜との間に形成された第2拡散防止膜と、
を具備することを特徴とする半導体装置。 - 前記第2領域のアスペクト比は、1.0から3.0である、
ことを特徴とする請求項1に記載の半導体装置。 - 半導体基板上に、前記半導体基板の表面に形成された接続領域を有する能動素子構造を形成する工程と、
前記半導体基板上に、底部が前記接続領域と接続された接続孔を有する第1絶縁膜を形成する工程と、
前記接続孔の側面と前記接続領域上とに第2拡散防止膜を形成する工程と、
前記第2拡散防止膜上であって、前記接続孔内の前記接続領域から第1高さまでの第1領域を、CoWまたはNiWを含む合金からなる第1導電膜を無電解めっきにより埋め込む工程と、
前記第1絶縁膜上に、底部が前記接続孔と接続された配線溝を有する第2絶縁膜を形成する工程と、
前記配線溝の内表面、前記接続孔の前記第1領域を除く第2領域の接続孔の側面、及び前記第1導電膜上とに第1拡散防止膜を形成する工程と、
前記第1拡散防止膜上であって、前記配線溝内、および前記接続孔の前記第1領域を除く第2領域内、を第2導電膜により埋め込む工程と、
を具備することを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003371005A JP4130621B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体装置およびその製造方法 |
US10/833,043 US7115999B2 (en) | 2003-10-30 | 2004-04-28 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003371005A JP4130621B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005136217A JP2005136217A (ja) | 2005-05-26 |
JP4130621B2 true JP4130621B2 (ja) | 2008-08-06 |
Family
ID=34543920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003371005A Expired - Fee Related JP4130621B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体装置およびその製造方法 |
Country Status (2)
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US (1) | US7115999B2 (ja) |
JP (1) | JP4130621B2 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050269709A1 (en) * | 2004-06-03 | 2005-12-08 | Agere Systems Inc. | Interconnect structure including tungsten nitride and a method of manufacture therefor |
US7329582B1 (en) * | 2005-06-15 | 2008-02-12 | Advanced Micro Devices, Inc. | Methods for fabricating a semiconductor device, which include selectively depositing an electrically conductive material |
US7629264B2 (en) * | 2008-04-09 | 2009-12-08 | International Business Machines Corporation | Structure and method for hybrid tungsten copper metal contact |
JP2013165224A (ja) * | 2012-02-13 | 2013-08-22 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
US11195798B2 (en) | 2014-07-25 | 2021-12-07 | Intel Corporation | Tungsten alloys in semiconductor devices |
US9966308B2 (en) | 2016-10-04 | 2018-05-08 | International Business Machines Corporation | Semiconductor device and method of forming the semiconductor device |
US10672649B2 (en) | 2017-11-08 | 2020-06-02 | International Business Machines Corporation | Advanced BEOL interconnect architecture |
US10269698B1 (en) | 2017-12-20 | 2019-04-23 | International Business Machines Corporation | Binary metallization structure for nanoscale dual damascene interconnects |
US11380581B2 (en) * | 2018-11-09 | 2022-07-05 | Globalfoundries U.S. Inc. | Interconnect structures of semiconductor devices having a via structure through an upper conductive line |
US11532550B2 (en) * | 2019-07-31 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure having a multi-layer conductive feature and method making the same |
US20210391438A1 (en) * | 2020-06-15 | 2021-12-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect Structure Having a Multi-Deck Conductive Feature and Method of Forming the Same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
JPH08153690A (ja) | 1994-09-29 | 1996-06-11 | Sony Corp | 半導体装置、半導体装置の製造方法、及び配線形成方法 |
JP3605291B2 (ja) | 1997-08-29 | 2004-12-22 | 株式会社日立製作所 | 半導体集積回路装置 |
US6319831B1 (en) * | 1999-03-18 | 2001-11-20 | Taiwan Semiconductor Manufacturing Company | Gap filling by two-step plating |
US6482656B1 (en) * | 2001-06-04 | 2002-11-19 | Advanced Micro Devices, Inc. | Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit |
JP2003100659A (ja) * | 2001-09-27 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US7294567B2 (en) * | 2002-03-11 | 2007-11-13 | Micron Technology, Inc. | Semiconductor contact device and method |
US6872659B2 (en) * | 2002-08-19 | 2005-03-29 | Micron Technology, Inc. | Activation of oxides for electroless plating |
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2003
- 2003-10-30 JP JP2003371005A patent/JP4130621B2/ja not_active Expired - Fee Related
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2004
- 2004-04-28 US US10/833,043 patent/US7115999B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US7115999B2 (en) | 2006-10-03 |
JP2005136217A (ja) | 2005-05-26 |
US20050093168A1 (en) | 2005-05-05 |
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