JP3480212B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3480212B2 JP3480212B2 JP167397A JP167397A JP3480212B2 JP 3480212 B2 JP3480212 B2 JP 3480212B2 JP 167397 A JP167397 A JP 167397A JP 167397 A JP167397 A JP 167397A JP 3480212 B2 JP3480212 B2 JP 3480212B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- semiconductor device
- resistive
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、高耐圧化を図る
ための抵抗性薄膜を有するパワーＩＣなどの横型の半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal type semiconductor device such as a power IC having a resistive thin film for increasing the breakdown voltage.
【０００２】[0002]
【従来の技術】パワーＩＣなどのプレーナ型の半導体装
置においては、高耐圧化を図るために、各種工夫がなさ
れてきた。その主なものはプレーナ接合（ｐｎ接合が内
部で曲がり、表面に露出している接合のこと）部の周辺
の空乏層（耐圧を維持する領域）を拡大させるために、
接合部の曲率を拡大したり、ガードリング（表面で空乏
層を拡大する作用をさせる）を配置したりすることによ
り、プレーナ接合部の電界強度を緩和する方法などがそ
れである。表面層の電界強度の緩和を目的とした電極構
造である所謂オーバーオキサイド構造もその一つであ
り、IEEE Trans.Electron Dev.ED-26,pp.1098 (1979)な
どにその最適化の方法が開示されている。また、抵抗性
窒化シリコン薄膜を電極間に被覆させ、電極に挟まれた
領域にかかる電位を抵抗で分割することにより、表面層
の電界緩和を実現する方法も開示されている。その文献
例としてはSolid-State Electronics,1972,Vol.15,pp.6
53-657などがある。この抵抗性窒化シリコン薄膜は、一
般にシリコンソースを電子ビームで蒸発させる、所謂電
子ビーム蒸着法で成膜したアモルファスＳｉ薄膜であ
る。このアモルファス成膜を形成する場合、シリコンソ
ースが高融点材料であるために、ソース溶融時に突沸が
生じやすく、成膜に突起が形成されるという不具合が発
生し、製造プロセスとしては課題が残る。2. Description of the Related Art Various improvements have been made in planar type semiconductor devices such as power ICs in order to increase the breakdown voltage. The main one is to expand the depletion layer (region for maintaining the breakdown voltage) around the planar junction (the junction where the pn junction bends inside and is exposed on the surface).
For example, a method of relaxing the electric field strength of the planar junction by increasing the curvature of the junction or arranging a guard ring (which causes the depletion layer to expand on the surface) is used. One of them is the so-called oxide structure, which is an electrode structure for the purpose of relaxing the electric field strength of the surface layer, and the optimization method is described in IEEE Trans.Electron Dev.ED-26, pp.1098 (1979). It is disclosed. Also disclosed is a method in which a resistive silicon nitride thin film is coated between electrodes and the potential applied to a region sandwiched between the electrodes is divided by a resistance to realize electric field relaxation of the surface layer. As an example of the literature, Solid-State Electronics, 1972, Vol. 15, pp. 6
There are 53-657 etc. This resistive silicon nitride thin film is an amorphous Si thin film formed by a so-called electron beam evaporation method, in which a silicon source is generally evaporated by an electron beam. When this amorphous film is formed, since the silicon source is a high melting point material, bumping is likely to occur when the source is melted, and projections are formed in the film formation, which remains a problem in the manufacturing process.
【０００３】この不具合を回避する手段として、Ｓｉタ
ーゲット（ソースのこと）を用いたスパッタ法によるア
モルファス薄膜があるが、この薄膜は一般に抵抗が低
く、そのため、電圧を印加した時の漏れ電流が大きくな
り、半導体装置の漏れ電流規格上適用が困難である場合
が多い。半絶縁膜を用いる技術（SIPOS;Semi-Insulatin
g Polycrystalline-Silicon)では減圧ＣＶＤ法でシラン
（SiH4) と亜酸化窒素（N2O)とをN2雰囲気下で反応さ
せ、通常６００℃以上で形成する。しかし、この方法は
６００℃以上という高温処理のためＡｌ電極形成後の成
膜は熱的に不可能であり、Ａｌ電極形成前に成膜しなけ
ればならないなどの制約がある。As a means for avoiding this inconvenience, there is an amorphous thin film formed by a sputtering method using a Si target (which means a source). However, this thin film generally has a low resistance, and therefore a large leak current is generated when a voltage is applied. In many cases, it is difficult to apply the semiconductor device according to the leakage current standard. Technology using semi-insulating film (SIPOS; Semi-Insulatin
In the case of g Polycrystalline-Silicon), silane (SiH 4 ) and nitrous oxide (N 2 O) are reacted in a N 2 atmosphere by a low pressure CVD method and usually formed at 600 ° C. or higher. However, since this method is a high-temperature treatment of 600 ° C. or higher, it is thermally impossible to form a film after forming the Al electrode, and there is a restriction that the film must be formed before forming the Al electrode.
【０００４】これ以外にプラズマＣＶＤ法を用いた窒化
シリコン薄膜をシリコンリッチな組成で成膜した抵抗性
窒化シリコン薄膜を用いる方法もある。図３は従来技術
で成膜した抵抗性窒化シリコン薄膜を有する半導体装置
の要部構成図である。ｐ形半導体基板１の表面層にｎウ
ェル領域２を形成し、ｎウェル領域２の表面層にｐベー
ス領域３を形成し、ｐベース領域３の表面層にｎ+ ソー
ス領域４を形成する。ｐベース領域３と離れてｎ+ ドレ
イン領域５をｎウェル領域２の表面層に形成する。ｎ+
ソース領域４に挟まれたｐベース領域３上とｎウェル領
域２上にゲート絶縁膜６を介してゲート電極９が形成さ
れる。ｎ+ ソース領域４とｎ+ ドレイン領域５とに挟ま
れたｐベース領域３上とｎウェル領域２上とに第１表面
保護膜１４であるＬＯＣＯＳ薄膜１０（局部酸化膜）と
ＰＳＧ薄膜１１（リンガラス薄膜）とが形成され、さら
にその上に抵抗性窒化シリコン薄膜１２が形成される。
またｎ+ ソース領域４上およびｎ+ ドレイン領域５上に
はソース電極７とドレイン電極８とが形成される。耐圧
を維持するための空乏層はｐベース領域３とｎ+ ドレイ
ン領域５の間のｎウェル領域に主に広がる。この空乏層
がシリコン内部（バルク）と同様にシリコンの表面層で
も均一に伸長するように、抵抗性窒化シリコン薄膜１２
を設けている。この半導体装置は６５０Ｖクラスの高耐
圧横型パワーＩＣで、その中の横型のＭＯＳＦＥＴ部を
図３では示した。In addition to this, there is also a method of using a resistive silicon nitride thin film formed by forming a silicon nitride thin film using a plasma CVD method with a silicon-rich composition. FIG. 3 is a main part configuration diagram of a semiconductor device having a resistive silicon nitride thin film formed by a conventional technique. An n well region 2 is formed on the surface layer of the p-type semiconductor substrate 1, a p base region 3 is formed on the surface layer of the n well region 2, and an n + source region 4 is formed on the surface layer of the p base region 3. An n + drain region 5 is formed in the surface layer of the n well region 2 apart from the p base region 3. n +
A gate electrode 9 is formed on p base region 3 and n well region 2 sandwiched by source region 4 with gate insulating film 6 interposed. On the p base region 3 and the n well region 2 sandwiched between the n + source region 4 and the n + drain region 5, the LOCOS thin film 10 (local oxide film) and the PSG thin film 11 (which are the first surface protection film 14) are formed. And a resistive silicon nitride thin film 12 are further formed thereon.
Source electrode 7 and drain electrode 8 are formed on n + source region 4 and n + drain region 5. The depletion layer for maintaining the breakdown voltage mainly spreads in the n well region between the p base region 3 and the n + drain region 5. The resistive silicon nitride thin film 12 is formed so that the depletion layer extends uniformly in the surface layer of silicon as well as in the silicon (bulk).
Is provided. This semiconductor device is a high breakdown voltage lateral power IC of 650 V class, and the lateral MOSFET portion therein is shown in FIG.
【０００５】[0005]
【発明が解決しようとする課題】前記の従来の方法で成
膜した抵抗性窒化シリコン薄膜１２は、つぎの実験でも
分かるように、耐圧に関して信頼性に課題がある。その
実験条件と実験結果とをつぎにに示す。
１）抵抗性窒化シリコン薄膜１２を形成した後、ポリイ
ミドを塗布し、プラスチック製ＤＩＬ（Ｄｕａｌ Ｉｎ
ｌｉｎｅ）パッケージで組立てる場合、（ａ）高温電
圧印加試験（Ｔa ＝１２５℃、ＶDSS ＝６６０Ｖ）で１
０時間以内に耐圧が６８０Ｖ（初期値）から４５０Ｖ付
近まで低下する。（ｂ）（ａ）の耐圧低下品を高温放置
（Ｔa ＝１５０℃）すると、６５時間後に耐圧が初期値
まで回復する。（ｃ）（ａ）の耐圧低下品を解体し、ポ
リイミドを除去して、セラミックパッケージに再組み立
てすると耐圧が初期値まで回復する。
２）抵抗性窒化シリコン薄膜１２を形成した後、樹脂
（プラスチック）モールドパッケージ（ＴＯ−２２０
Ｆ）で組み立てる場合、（ａ）高温電圧印加試験（Ｔa
＝１２５℃、ＶDSS ＝６６０Ｖ）で１０時間以内に耐圧
が低下する。（ｂ）（ａ）の耐圧低下品を高温放置（Ｔ
a ＝１５０℃）すると、６５時間後に耐圧が初期値まで
回復する。The resistive silicon nitride thin film 12 formed by the above-mentioned conventional method has a problem with respect to withstand voltage, as will be understood from the following experiment. The experimental conditions and experimental results are shown below. 1) After the resistive silicon nitride thin film 12 is formed, polyimide is applied to the DIL (Dual In
(a) High temperature voltage application test (T a = 125 ° C, V DSS = 660V)
The breakdown voltage drops from 680V (initial value) to around 450V within 0 hours. (B) When the low breakdown voltage product of (a) is left at high temperature (T a = 150 ° C.), the breakdown voltage recovers to the initial value after 65 hours. (C) When the withstand voltage-reduced product of (a) is disassembled, the polyimide is removed, and the ceramic package is reassembled, the withstand voltage is restored to the initial value. 2) After forming the resistive silicon nitride thin film 12, a resin (plastic) mold package (TO-220)
When assembled in F), (a) High temperature voltage application test ( Ta
= 125 ° C., V DSS = 660 V), the breakdown voltage decreases within 10 hours. (B) The product with reduced withstand voltage of (a) is left at high temperature (T
a = 150 ° C.), the withstand voltage recovers to the initial value after 65 hours.
【０００６】この耐圧劣化および回復のメカニズムはつ
ぎのように説明される。
１）抵抗性窒化シリコン薄膜は化学量論組成から大幅に
ずれた条件下では、つまりＳｉX Ｎy Ｈz の組成式で、
しかもｘ＞＞ｙ，ｚの条件（シリコンリッチ）で成膜さ
れた薄膜はdisordered phase（規則的配列からずれた配
列状態）を多く含む膜である。
２）disordered phaseとはつぎに示す３つの化学結合種
をタイプとするもの（タイプ（１）、タイプ（２）およ
びタイプ（３））であり、その中でバンドギャップ（禁
制帯）内に準位をつくるものはタイプ（２）（価電子帯
より0.5eV 上）とタイプ（３）（伝導帯より0.3eV 下）
であることが知られている〔J.Appl.Phs.,58(3),pp.124
8 (1985)〕。The mechanism of this breakdown voltage recovery and recovery is explained as follows. 1) The resistive silicon nitride thin film is under the condition that the stoichiometric composition is largely deviated, that is, the composition formula of Si X N y H z ,
Moreover, the thin film formed under the conditions of x >> y and z (silicon rich) contains a large amount of disordered phase (arranged state deviated from regular arrangement). 2) Disordered phase is a type (type (1), type (2) and type (3)) of the following three types of chemical bonds, in which the levels within the band gap (forbidden band) The ones that make up are type (2) (0.5eV above the valence band) and type (3) (0.3eV below the conduction band)
(J. Appl. Phs., 58 (3), pp.124
8 (1985)].
【０００７】[0007]
【化１】 [Chemical 1]
【０００８】３）タイプ（２）とタイプ（３）の変換は
図４に示すように水素原子の吸脱着で起こる（≡Si-Hの
結合エネルギーは295.7KJ/mol)。このタイプ（２）とタ
イプ（３）の変換が可逆的に起こることで、前記の耐圧
の劣化と回復が起こり、信頼性に関して不具合を生じ
る。この発明の目的は、前記の課題を解決して、耐圧に
関して高信頼性の半導体装置を提供することにある。3) Conversion between type (2) and type (3) occurs by adsorption and desorption of hydrogen atoms as shown in FIG. 4 (bonding energy of ≡Si-H is 295.7 KJ / mol). The reversible conversion between the type (2) and the type (3) causes the breakdown voltage to be deteriorated and recovered, causing a problem in reliability. An object of the present invention is to solve the above problems and provide a highly reliable semiconductor device with respect to breakdown voltage.
【０００９】[0009]
【課題を解決するための手段】前記の目的を達成するた
めに、半導体基板内にｐｎ接合を有し、該ｐｎ接合の端
部が前記半導体基板の表面に露出しており、該露出部上
に第１表面保護膜と、シリコン（Ｓｉ）、窒素（Ｎ）お
よび水素（Ｈ）を主成分とする抵抗性窒化シリコン薄膜
とが積層されて被覆される半導体装置において、該抵抗
性窒化シリコン薄膜上にＳｉ−Ｈの結合エネルギーより
も大きな結合エネルギーを有する第２表面保護膜が形成
される構造とする。In order to achieve the above object, a pn junction is provided in a semiconductor substrate, and an end portion of the pn junction is exposed on a surface of the semiconductor substrate. In a semiconductor device in which a first surface protective film and a resistive silicon nitride thin film containing silicon (Si), nitrogen (N) and hydrogen (H) as main components are laminated and covered, the resistive silicon nitride thin film is provided. The structure is such that the second surface protective film having a binding energy larger than that of Si—H is formed thereon.
【００１０】前記の第２表面保護膜が水素化物の薄膜で
あるとよい。またこの水素化物の膜が少なくとも炭素
（Ｃ）と水素（Ｈ）を主成分とするＣX Ｈy の組成を有
する薄膜であると効果的である。前記の第２表面保護膜
が、Ｓｉ−Ｆ結合を有する薄膜か、またはＳｉ−Ｆ結合
とＣ−Ｈ結合を有する薄膜であるとよい。The second surface protective film is preferably a thin film of hydride. It is also effective that the hydride film is a thin film having a composition of C X H y containing at least carbon (C) and hydrogen (H) as main components. The second surface protection film may be a thin film having a Si—F bond or a thin film having a Si—F bond and a C—H bond.
【００１１】このように、Ｓｉ−Ｈ（≡Ｓｉ−Ｈのこ
と）の結合エネルギー（295.7KJ/mol)より大きな、つま
り安定な水素結合（−Ｃ−Ｈ；411.6KJ/mol)またはさら
に安定なＳｉの終端結合が例えばＳｉ−Ｆ結合（543.1K
J/mol)をもつ薄膜で被覆することで、前記の抵抗性窒化
シリコン薄膜を構成するタイプ（２）とタイプ（３）と
が安定化され、薄膜全体が安定に保たれる。Thus, the bond energy (--C--H; 411.6 KJ / mol), which is larger than the binding energy (295.7 KJ / mol) of Si--H (.ident.Si--H), is stable. The termination bond of Si is, for example, Si-F bond (543.1K
By coating with a thin film having J / mol), the types (2) and (3) constituting the resistive silicon nitride thin film are stabilized, and the entire thin film is kept stable.
【００１２】つまり、前記の組成の第２表面保護膜を被
覆することで、抵抗性窒化シリコン薄膜が安定化して、
耐圧信頼性が向上する。また、ｐｎ接合を有し、少なく
とも該ｐｎ接合の露出面に表面保護膜が形成され、該表
面保護膜上にＳｉ−Ｈの結合エネルギーよりも大きな結
合エネルギーを有する抵抗性薄膜が形成される構造とす
る。この抵抗性薄膜の組成が、炭素（Ｃ）元素を含み、
Ｓｉ、Ｎ、Ｈ、Ｆ（フッ素）のうち少なくとも一つの元
素からなるようにするとよい。That is, by coating the second surface protective film having the above composition, the resistive silicon nitride thin film is stabilized,
Withstand voltage reliability is improved. Further, a structure having a pn junction, a surface protective film is formed on at least an exposed surface of the pn junction, and a resistive thin film having a binding energy larger than that of Si—H is formed on the surface protective film. And The composition of the resistive thin film contains a carbon (C) element,
It is preferable to be composed of at least one element of Si, N, H, and F (fluorine).
【００１３】このように、耐圧的に不安定な抵抗性窒化
シリコン薄膜をこの発明の抵抗性薄膜に代えることで高
信頼性化を図ることができる。As described above, by replacing the resistive silicon nitride thin film which is unstable in pressure resistance with the resistive thin film of the present invention, high reliability can be achieved.
【００１４】[0014]
前記の第２表面保護膜１３として、Ｃx Ｈy 薄膜を０．
１μｍプラズマＣＶＤ法で成膜する。その成膜条件はCH
4/H2=15/85SCCM、基板温度300 ℃、Ｐ=10Pa 、ＲＦ=1kW
である。この条件で試作した半導体装置をタイプＩとす
る。
〔実施例２〕
前記の第２表面保護膜１３として、Ｓｉx Ｃy Ｆz 薄膜
を０．１μｍプラズマＣＶＤ法で成膜する。これを半導
体装置タイプIIとする。As the second surface protective film 13, a Cx Hy thin film of 0.
A film is formed by a 1 μm plasma CVD method. The film forming condition is CH
4 / H 2 = 15 / 85SCCM, substrate temperature 300 ℃, P = 10Pa, RF = 1kW
Is. A semiconductor device prototyped under these conditions is called type I. Example 2 As the second surface protection film 13, a Six Cy Fz thin film is formed by a 0.1 μm plasma CVD method. This is referred to as a semiconductor device type II.
【００１５】尚、タイプＩおよびタイプIIの半導体装置
とも、６５０Ｖクラスの高耐圧横型パワーＩＣである。
また、図１は高耐圧横型パワーＩＣの中の横型ＭＯＳＦ
ＥＴ部を示した図である。図１において、耐圧を維持す
るための空乏層はｐベース領域３とｎ+ ドレイン領域５
の間のｎウェル領域に主に広がる。電圧をｎ+ ソース領
域４およびｎ+ ドレイン領域間に印加すると、抵抗性窒
化シリコン薄膜１２内に極微小な電流が流れて、抵抗性
窒化シリコン薄膜１２内の電位分布が均一化される。そ
の影響で、シリコン内部（バルク）に形成される空乏層
と同様にシリコン表面層に形成される空乏層も均一に伸
長する。しかし、抵抗性窒化シリコン膜１２は前記のよ
うに耐圧安定性（信頼性）に問題があり、実施例１およ
び実施例２で示したように、この抵抗性窒化シリコン薄
膜１２上にＳｉ−Ｈの結合エネルギーよりも大きな結合
エネルギーを有する第２表面保護膜を被覆することで耐
圧の安定性（信頼性）が確保される。Both the type I and type II semiconductor devices are high-voltage lateral power ICs of 650V class.
Further, FIG. 1 shows a lateral MOSF in a high voltage lateral power IC.
It is the figure which showed the ET section. In FIG. 1, the depletion layer for maintaining the breakdown voltage is the p base region 3 and the n + drain region 5.
Mainly extends to the n-well region between. When a voltage is applied between the n + source region 4 and the n + drain region, a very small current flows in the resistive silicon nitride thin film 12 and the potential distribution in the resistive silicon nitride thin film 12 is made uniform. Due to the influence, the depletion layer formed in the silicon surface layer as well as the depletion layer formed in the silicon (bulk) uniformly extends. However, as described above, the resistive silicon nitride film 12 has a problem in withstand voltage stability (reliability), and as shown in Examples 1 and 2, Si-H is formed on the resistive silicon nitride thin film 12. The stability (reliability) of the breakdown voltage is secured by coating the second surface protective film having a binding energy larger than the binding energy of.
【００１６】図２は本発明品と従来品の高温電圧印加試
験の結果を比較して示したものである。本発明品である
２つのタイプ（タイプＩとタイプII) のものをプラスチ
ックモールド（Ｔ０−２２０Ｆ）に組み込んで、前述と
同様の高温電圧印加試験（Ｔa＝１２５℃、ＶDSS ＝６
６０Ｖ）を実施した。その結果２００時間経過しても耐
圧劣化は生じていない。それに対して従来品は１０時間
以内で耐圧劣化を起こす。この耐圧劣化は前記したメカ
ニズムで説明できることがこの結果から裏付けられた。FIG. 2 shows a comparison of the results of the high temperature voltage application test of the product of the present invention and the conventional product. Two types of the present invention (type I and type II) were incorporated into a plastic mold (T0-220F), and the same high temperature voltage application test (T a = 125 ° C., V DSS = 6) as described above was performed.
60V) was carried out. As a result, the breakdown voltage did not deteriorate even after 200 hours had passed. On the other hand, the conventional product deteriorates in withstand voltage within 10 hours. From this result, it is supported that the breakdown voltage can be explained by the mechanism described above.
【００１７】ここでは図による説明は省略するが、この
発明の他の実施例として、従来の抵抗性窒化シリコン薄
膜１２をＳｉ−Ｈの結合エネルギーよりも大きな結合エ
ネルギーを有する抵抗性薄膜に置き換えることで、全く
同様の結果が得られた。この抵抗性薄膜の例を挙げれ
ば、Ｓｉ、Ｎ、Ｈ、Ｃ、ＦからなるＳｉＮ−ｌｉｋｅの
薄膜やＨ、Ｃからなるｄｉａｍｏｎｄ−ｌｉｋｅの薄膜
やＨ、Ｃ、ＦからなるＦ入りのｄｉａｍｏｎｄ−ｌｉｋ
ｅの薄膜などである。尚、この抵抗性薄膜は表面保護膜
の働きもすることは勿論である。Although not described here with reference to the drawings, as another embodiment of the present invention, the conventional resistive silicon nitride thin film 12 has a bond energy larger than the bond energy of Si--H.
Substituting a resistive thin film with energy gave exactly the same results. To give an example of this resistive thin film, a SiN-like thin film made of Si, N, H, C, F, a diamond-like thin film made of H, C, or a F-containing diamond-made of H, C, F is used. lik
e thin film and the like. Of course, this resistive thin film also functions as a surface protective film.
【００１８】[0018]
【発明の効果】この発明によれば、Ｓｉ−Ｈの結合より
大きな水素との結合エネルギーを有する水素化物などの
薄膜を従来の抵抗性窒素シリコン薄膜上に被覆すること
で、高耐圧横型半導体装置の耐圧特性を安定させること
ができる。また、従来の抵抗性窒化シリコン薄膜をＳｉ
−Ｈの結合より大きな水素との結合エネルギーを有す抵
抗性薄膜に置き換えることで、耐圧特性を安定化させる
ことができる。According to the present invention, by coating a conventional resistive nitrogen silicon thin film with a thin film of hydride or the like having a binding energy with hydrogen larger than that of Si-H, a high breakdown voltage lateral semiconductor device can be obtained. It is possible to stabilize the withstand voltage characteristic of. In addition, the conventional resistive silicon nitride thin film is
The withstand voltage characteristic can be stabilized by replacing with a resistive thin film having a binding energy with hydrogen larger than the —H bond.
【図１】この発明の実施例の要部構成図FIG. 1 is a configuration diagram of a main part of an embodiment of the present invention.
【図２】本発明品と従来品の高温電圧印加試験の結果を
比較した図FIG. 2 is a diagram comparing the results of high temperature voltage application tests of the product of the present invention and the conventional product
【図３】従来の抵抗性窒化シリコン薄膜を有する半導体
装置の要部構成図FIG. 3 is a main part configuration diagram of a semiconductor device having a conventional resistive silicon nitride thin film.
【図４】タイプ（２）とタイプ（３）の変換を示す図FIG. 4 is a diagram showing conversion between type (2) and type (3).
１ ｐ形半導体基板 ２ ｎウェル領域 ３ ｐベース領域 ４ ｎ+ ソース領域 ５ ｎ+ ドレイン領域 ６ ゲート絶縁膜 ７ ソース電極 ８ ドレイン電極 ９ ゲート電極 １０ ＬＯＣＯＳ薄膜 １１ ＰＳＧ薄膜 １２ 抵抗性窒化シリコン薄膜 １３ 第２表面保護膜 １４ 第１表面保護膜1 p-type semiconductor substrate 2 n well region 3 p base region 4 n + source region 5 n + drain region 6 gate insulating film 7 source electrode 8 drain electrode 9 gate electrode 10 LOCOS thin film 11 PSG thin film 12 resistive silicon nitride thin film 13 2 Surface protective film 14 First surface protective film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/314 - 1/318 H01L 29/06 H01L 29/78 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/314-1/318 H01L 29/06 H01L 29/78
Claims (6)
合の端部が前記半導体基板の表面に露出しており、該露
出部上に第１表面保護膜と、シリコン（Ｓｉ）、窒素
（Ｎ）および水素（Ｈ）を主成分とする抵抗性窒化シリ
コン薄膜とが積層されて被覆される半導体装置におい
て、該抵抗性窒化シリコン薄膜上にＳｉ−Ｈの結合エネ
ルギーよりも大きな結合エネルギーを有する第２表面保
護膜が形成されることを特徴とする半導体装置。1. A semiconductor substrate having a pn junction, an end portion of the pn junction is exposed on a surface of the semiconductor substrate, and a first surface protective film and silicon (Si) are provided on the exposed portion. In a semiconductor device in which a resistive silicon nitride thin film containing nitrogen (N) and hydrogen (H) as a main component is laminated and covered, a binding energy larger than the binding energy of Si-H on the resistive silicon nitride thin film. A second surface protection film having: is formed.
ことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the second surface protective film is a thin film of hydride.
と水素（Ｈ）を主成分とするＣx Ｈy の組成を有する薄
膜であることを特徴とする請求項２記載の半導体装置。3. A thin film of hydride comprises at least carbon (C).
3. The semiconductor device according to claim 2, which is a thin film having a composition of Cx Hy containing hydrogen and hydrogen as main components.
薄膜であることを特徴とする請求項１記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the second surface protection film is a thin film having a Si—F bond.
結合とを有する薄膜であることを特徴とする請求項１記
載の半導体装置。5. The second surface protection film comprises Si—F bonds and C—H.
The semiconductor device according to claim 1, which is a thin film having a bond.
露出面に表面保護膜が形成され、該表面保護膜上にＳｉ
−Ｈの結合エネルギーよりも大きな結合エネルギーを有
するＨ、Ｃ元素を含み、Ｓｉ、Ｎ、Ｆのうち少なくとも
１つの元素からなる抵抗性薄膜が形成されることを特徴
とする半導体装置。6. A pn junction, a surface protective film is formed on at least an exposed surface of the pn junction, and Si is formed on the surface protective film.
At least one of Si, N, and F containing H and C elements having a binding energy larger than that of -H.
A semiconductor device having a resistive thin film formed of one element .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP167397A JP3480212B2 (en) | 1997-01-08 | 1997-01-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP167397A JP3480212B2 (en) | 1997-01-08 | 1997-01-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10199879A JPH10199879A (en) | 1998-07-31 |
| JP3480212B2 true JP3480212B2 (en) | 2003-12-15 |
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ID=11508047
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP167397A Expired - Fee Related JP3480212B2 (en) | 1997-01-08 | 1997-01-08 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3480212B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5867814B2 (en) * | 2012-01-13 | 2016-02-24 | 住友電工デバイス・イノベーション株式会社 | Manufacturing method of semiconductor device |
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|---|---|
| JPH10199879A (en) | 1998-07-31 |
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