JP2887501B2 - Equalization method - Google Patents
Equalization methodInfo
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- JP2887501B2 JP2887501B2 JP2130752A JP13075290A JP2887501B2 JP 2887501 B2 JP2887501 B2 JP 2887501B2 JP 2130752 A JP2130752 A JP 2130752A JP 13075290 A JP13075290 A JP 13075290A JP 2887501 B2 JP2887501 B2 JP 2887501B2
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- delay
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は等化方法に関する。The present invention relates to an equalization method.
本発明は、複数の遅延手段の直列回路に入力信号を供
給し、その入力信号及び各遅延手段の遅延出力信号に係
数を乗算して加算して、等化出力信号を得るようにした
等化方式において、入力信号を複数の遅延手段の直列回
路に供給して、その直列回路内を正方向に伝送させて順
次遅延させ、その後、入力信号を直列回路内を逆方向に
伝送させて順次遅延させ、その後、入力信号を直列回路
内を正方向に伝送させて順次遅延させると共に、出力等
化信号の振幅誤差を検出し、その検出された振幅誤差に
応じて、その振幅誤差が最小と成るように、入力信号及
び各遅延手段の遅延出力信号に夫々乗算する係数を演算
するようにしたことにより、出力等化信号の振幅誤差を
補正することができると共に、入力信号の継続時間が短
ったり、入力信号にプリアンブルがなくても、等化出力
信号における、入力信号の当初の信号部分に対応する信
号部分の欠如の虞がなく成るようにしたものである。The present invention provides an equalization in which an input signal is supplied to a series circuit of a plurality of delay means, and the input signal and a delay output signal of each delay means are multiplied by a coefficient and added to obtain an equalized output signal. In the method, an input signal is supplied to a series circuit of a plurality of delay means, transmitted in the series circuit in the forward direction and sequentially delayed, and then the input signal is transmitted in the reverse direction in the series circuit and sequentially delayed. After that, the input signal is transmitted in the positive direction in the serial circuit and is sequentially delayed, and the amplitude error of the output equalized signal is detected. According to the detected amplitude error, the amplitude error is minimized. As described above, by calculating the coefficient for multiplying the input signal and the delay output signal of each delay means, the amplitude error of the output equalized signal can be corrected and the duration of the input signal can be shortened. Or input signal Preamble even without, in the equalization output signal, it is obtained as comprising no portions of the lack of signal portions corresponding to the original signal portion of the input signal.
基地局（固定局）と移動局（自動車電話機）との間を
電波で結ぶデジタルセルラー通信方式の一つに、タイム
・ディビジョン・マルチプル・アクセス方式があるが、
この方式では、900MHz帯の各チャンネル毎に、例えば、
６個の受信スロットを設け、その内の１個のスロットの
受信信号を、120msec毎に、20msecずつ受信し、又、各
チャンネル毎に、同様に、６個の送信スロットを設け、
その内の１個のスロットの送信信号を送信するようにし
ている。この場合、基準受信キャリア周波数及び基準送
信キャリア周波数は互いに異なっている。One of the digital cellular communication systems that connects a base station (fixed station) and a mobile station (car phone) by radio waves is a time division multiple access system.
In this method, for each channel of the 900 MHz band, for example,
Six reception slots are provided, and a reception signal of one of the slots is received every 20 msec every 120 msec, and similarly, six transmission slots are provided for each channel,
The transmission signal of one of the slots is transmitted. In this case, the reference reception carrier frequency and the reference transmission carrier frequency are different from each other.
ところで、基地局又は移動局において、受信信号を等
化装置を用いて等化しようとする場合、受信信号の継続
時間が、頗る短い（上述の場合は、20msec）のために、
等化出力信号応における、受信信号の当初の信号部分に
対応する信号部分が欠如する虞があった。By the way, in a base station or a mobile station, when trying to equalize a received signal using an equalizer, the duration of the received signal is extremely short (20 msec in the above case).
In the case of the equalized output signal, there is a possibility that a signal part corresponding to the original signal part of the received signal may be missing.
かかる点に鑑み、本発明は、出力等化信号の振幅誤差
を補正することができると共に、入力信号の継続時間が
短ったり、入力信号にプリアンブルがなくても、等化出
力信号における、入力信号の当初の信号部分に対応する
信号部分の欠如の虞がなく成る等化方法を提案しようと
するものである。In view of such a point, the present invention can correct the amplitude error of the output equalized signal, and can reduce the input time in the equalized output signal even if the duration of the input signal is short or the input signal does not have a preamble. It is an object of the invention to propose an equalization method which eliminates the risk of lack of a signal part corresponding to the original signal part of the signal.
本発明による等化方法は、入力端子からの入力信号の
１サンプリング周期に等しい遅延量を有する初段乃至最
終段の複数ｎ段の遅延手段と、入力信号及びｎ段の遅延
手段の各出力信号に係数を乗算する（ｎ＋１）個の係数
乗算手段と、その（ｎ＋１）個の係数乗算手段の出力を
加算する加算手段と、その加算手段からの出力等化信号
に基づいて、その出力等化信号の振幅誤差を推定する誤
差推定手段と、その誤差推定手段からの判定信号に基づ
いて、振幅誤差が最小となるような各別の係数信号を形
成して、（ｎ＋１）個の係数乗算手段にそれぞれ供給す
るタップゲイン調整手段と、初段の遅延手段及び最終段
の遅延手段からそれぞれはみ出した入力信号のサンプリ
ング信号をそれぞれ記憶する記憶手段とを備える等化フ
ィルタ手段を使用する。The equalization method according to the present invention includes a plurality of n-stage delay units of a first stage to a last stage having a delay amount equal to one sampling period of an input signal from an input terminal, and an input signal and each output signal of the n-stage delay unit. (N + 1) coefficient multiplication means for multiplying the coefficient, addition means for adding the outputs of the (n + 1) coefficient multiplication means, and an output equalized signal based on the output equalized signal from the addition means Estimating means for estimating the amplitude error of each of the above, and based on the determination signal from the error estimating means, forming each of the different coefficient signals such that the amplitude error is minimized. An equalizing filter means is provided which includes tap gain adjusting means for supplying the signals, and storage means for storing sampling signals of the input signals protruding from the delay means at the first stage and the delay means at the last stage. .
そして、入力信号を構成する連続するｍ個（但し、ｍ
＞ｎ）のサンプリング信号を入力端子に供給して、ｎ段
の遅延手段を初段の遅延手段から最終段の遅延手段に向
かって正方向に伝送させて順次遅延させ、その後、ｎ段
の遅延手段を最終段の遅延手段から初段の遅延手段に向
かって逆方向に伝送させて順次遅延させ、その後、ｎ段
の遅延手段を初段の遅延手段から最終段の遅延手段に向
かって正方向に伝送させて順次遅延させるようにする。Then, the continuous m pieces (where m
> N) is supplied to the input terminal, and the n-stage delay means are transmitted in the forward direction from the first-stage delay means to the last-stage delay means to be sequentially delayed, and then the n-stage delay means Are transmitted in the reverse direction from the last stage delay means to the first stage delay means and are sequentially delayed, and then the n stage delay means are transmitted in the forward direction from the first stage delay means to the last stage delay means. So that they are sequentially delayed.
以下に、第１図を参照して、本発明の実施例を詳細に
説明しよう。この実施例は、上述した基地局（固定局）
と移動局（自動車電話機）との間を結ぶタイム・ディビ
ジョン・マルチプル・アクセス方式のデジタル通信方式
に、本発明を適用した場合で、900MHz帯の各チャンネル
毎に、例えば、６個の受信スロットを設け、その内の１
個のスロットの受信信号を、120msec毎に、20msecずつ
受信し、又、各チャンネル毎に、同様に、６個の送信ス
ロットを設け、その内の１個のスロットの送信信号を送
信するようにしている。この場合、基準受信キャリア周
波数及び基準送信キャリア周波数は互いに異なってい
る。Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. This embodiment is based on the base station (fixed station) described above.
In a case where the present invention is applied to a digital communication system of a time division multiple access system connecting a mobile station (mobile telephone) and a mobile station (car telephone), for example, six reception slots are provided for each channel in the 900 MHz band. And one of them
The received signals of the 20 slots are received every 20 msec every 120 msec. Similarly, six transmission slots are provided for each channel, and the transmission signal of one of the slots is transmitted. ing. In this case, the reference reception carrier frequency and the reference transmission carrier frequency are different from each other.
第１図は、例えば、移動局（自動車電話機）の送受信
装置における、デジタル・シグナル・プロセッサのファ
ームウエアによる信号処理（演算処理）を、回路形式で
図示したものであるが、かかる信号処理を、第１図に図
示のハード（ディスクリート回路又はIC）にても行い得
ることは勿論である。FIG. 1 illustrates, in a circuit form, signal processing (arithmetic processing) by firmware of a digital signal processor in a transmitting / receiving apparatus of a mobile station (car phone), for example. Of course, it can be performed by the hardware (discrete circuit or IC) shown in FIG.
（12）は等化フィルタ部で、（11）はその入力端子で
ある。入力端子（11）には、入力信号（継続時間が20ms
ecである１スロットの受信信号）（入力データ信号）が
供給される。(12) is an equalization filter unit, and (11) is its input terminal. The input terminal (11) receives an input signal (duration: 20 ms
ec, a received signal of one slot) (input data signal).
この等化フィルタ部（12）は、遅延量が共に入力信号
の１サンプリング周期Tsに等しい遅延手段D1、D2、・・
・・、Dmの直列回路と、入力信号及び各遅延手段D1、
D2、・・・、Dmの遅延出力信号が夫々供給される係数乗
算手段M0、M1、・・・、Mmと、各係数乗算手段M0、M1、
・・・・、Mmの乗算出力が夫々供給されて、順次累積加
算される加算手段A1、A2、・・・・・、Amとから構成さ
れ、加算手段Amから等化出力信号（等化出力データ信
号）が得られて、出力端子（13）から出力されるように
成されている。The equalizing filter section (12) includes delay means D 1 , D 2 ,... Each having a delay amount equal to one sampling period Ts of the input signal.
.., a series circuit of Dm, an input signal and each delay means D 1 ,
D 2, · · ·, coefficient multiplying means M 0 for delayed output signal of Dm are respectively supplied, M 1, ···, and Mm, the coefficient multiplying means M 0, M 1,
,..., Am are provided, and multiplied outputs of Mm are respectively supplied and sequentially added and accumulated. The addition means A 1 , A 2 ,... The output data signal is output from the output terminal (13).
（14）は誤差推定部（誤差推定手段）で、等化フィル
タ部（12）の加算器Mmからの等化出力信号が供給され
て、判定信号が出力される。(14) is an error estimating unit (error estimating means) which is supplied with an equalized output signal from the adder Mm of the equalizing filter unit (12) and outputs a judgment signal.
TGはタップゲイン調整部（タップゲイン調整手段）
で、誤差推定部（13）から判定信号が供給されて、振幅
誤差が最小となるような各係数乗算手段M0、M1、M2、・
・・・・・・、Mmに夫々各別に供給する係数信号が形成
される。TG is tap gain adjuster (tap gain adjuster)
The determination signal is supplied from the error estimating unit (13), and each of the coefficient multiplying means M 0 , M 1 , M 2 ,.
... A coefficient signal to be supplied to each of Mm is formed.
しかして、入力信号を複数の遅延手段D1、D2、・・・
・、Dmの直列回路に供給して、その直列回路内を正方向
に伝送させて順次遅延させ、その後、入力信号を直列回
路内を逆方向に伝送させて順次遅延させ、その後、入力
信号を直列回路内を正方向に伝送させて順次遅延させる
ようにする。これを第２図を参照して具体的に説明す
る。Thus, the input signal is divided into a plurality of delay means D 1 , D 2 ,.
・ Supply to the serial circuit of Dm, transmit in the serial circuit in the forward direction and delay sequentially, and then transmit the input signal in the reverse direction in the serial circuit and delay sequentially. The signal is transmitted in the positive direction in the series circuit and is sequentially delayed. This will be specifically described with reference to FIG.
ここで、１スロットの受信信号から成る入力信号が、
サンプリング信号X0、X1、X2、・・・・・・、Xnの連続
から構成されているものとする。尚、ｎはｍより大きな
数である。Here, the input signal composed of the received signal of one slot is
Assume that the sampling signal is composed of a sequence of X 0 , X 1 , X 2 ,..., Xn. Note that n is a number larger than m.
又、図示を省略するも、入力端子（11）側及び最終段
の遅延手段Dmの出力側には、入力信号を構成するサンプ
リング信号X0、X1、X2、・・・・、Xnの、遅延手段D1、
D2、・・・・、Dmの直列回路の両側からはみ出したサン
プリング信号を記憶する所定容量の記憶手段が設けられ
ている。Although not shown, the sampling signals X 0 , X 1 , X 2 ,..., Xn constituting the input signal are provided on the input terminal (11) side and the output side of the delay means Dm in the final stage. , Delay means D 1 ,
Storage means of a predetermined capacity for storing sampling signals protruding from both sides of the series circuit of D 2 ,..., Dm is provided.
先ず、入力信号（11）に、この入力信号をサンプリン
グ信号X0、X1、X2、・・、Xnの順に供給する。かくする
と、ある時点で、第２図Ａに示す如く、遅延手段Dm
−１、Dm−２、・・、D2、D1の各出力側及び入力端子
（11）には、サンプリング信号X0、X1、・・・、Xm
−３、Xm−２、Xm−１が夫々出力され、遂には、第２図
Ｂに示す如く、遅延手段Dm、Dm−１、・・・・・・、
D2、D1の各出力側及び入力端子（11）に、夫々サンプリ
ング信号Xn−ｍ、Xn−ｍ＋１、・・・、Xn−２、Xn
−１、Xnが出力された時点で、各サンプリング信号の伝
送方向が逆転せしめられる。First, this input signal is supplied to the input signal (11) in the order of the sampling signals X 0 , X 1 , X 2 ,..., Xn. Thus, at some point, as shown in FIG.
−1 , Dm− 2 ,..., D 2 , D 1 are provided on the output side and the input terminal (11) with sampling signals X 0 , X 1 ,.
-3 , Xm- 2 , Xm- 1 are output respectively, and finally, as shown in FIG. 2B, delay means Dm, Dm- 1 ,.
D 2, to the output side and the input terminal of the D 1 (11), respectively the sampling signal Xn-m, Xn-m + 1, ···, Xn- 2, Xn
At the point when 1 , Xn is output, the transmission direction of each sampling signal is reversed.
かくすると、その後のある時点で、第２図Ｃに示す如
く、遅延手段Dm、Dm−１、・・・・・・・、D2、D1の各
出力側及び入力端子（11）には、サンプリング信号Xn−
ｍ−２、Xn−ｍ−１、・・・・・、Xn−４、Xn−３、Xn
−２が出力され、遂には、第２図Ｄに示す如く、遅延手
段Dm、Dm1、・・・・・、D2、D1の各出力側及び入力端
子（11）に、夫々サンプリング信号X0、X1、・・・、Xm
−２、Xm−１、Xmが出力された時点で、各サンプリング
信号の伝送方向が更に逆転せしめられる。When Thus, at some later time, as shown in FIG. 2 C, delay means Dm, Dm- 1, · · · · · · ·, D 2, to the output side and the input terminal of the D 1 (11) is , The sampling signal Xn−
m- 2 , Xn-m- 1 , ..., Xn- 4 , Xn- 3 , Xn
- 2 is output, and finally, as shown in FIG. 2 D, and delay means Dm, Dm 1, · · · · ·, each of the output side and the input terminal of the D 2, D 1 (11) , respectively sampled signal X 0 , X 1 , ..., Xm
- 2, xm- 1, when Xm is output, the transmission direction of each sampling signal is made to further reverse rotation.
かくすると、ある時点で、第２図Ｅに示す如く、遅延
手段Dm、Dm−１、・・・・、D2、D1の各出力側及び入力
端子（11）には、サンプリング信号X2、X3、・・・・
・、Xm、Xm＋１、Xm＋２が夫々出力され、遂には、第２
図Ｆに示す如く、遅延手段Dm、Dm−１、・・・・・、
D2、D1の各出力側及び入力端子（11）に、夫々サンプリ
ング信号Xn−ｍ、Xn−ｍ＋１、・・・・・、Xn−２、Xn
−１、Xnが出力された時点で等化は終了する。When Thus, at some point, as shown in Fig. 2 E, delay means Dm, Dm- 1, · · · ·, to the output side and the input terminal of the D 2, D 1 (11), the sampling signal X 2 , X 3 , ...
, Xm, Xm + 1 and Xm + 2 are output respectively, and finally the second
As shown in FIG. F, delay means Dm, Dm- 1 ,...
The sampling signals Xn−m, Xn−m + 1 ,..., Xn− 2 , Xn are respectively applied to the output side of D 2 and D 1 and the input terminal (11).
- 1, equalization when Xn is output ends.
尚、この場合には、入力信号が遅延手段D1、D2、・・
・・Dm−１、Dmの直列回路を１往復してから、等化出力
信号において、入力信号の当初の信号部分に対応する信
号部分の欠如の虞のない等化を行うが、入力信号の往復
回数は２回以上でも良い。In this case, the input signal is delayed by delay means D 1 , D 2 ,.
· · Dm- 1, Dm the series circuit from when one round trip, the equalized output signal, performs the risk-free equalization of lack of signal portions corresponding to the original signal portion of the input signal, the input signal The number of reciprocations may be two or more.
次に、第３図を参照して、本実施例で用いられるπ/4
シフテッド・クォードラチャ・フェイズ・キーイング変
調方式の変調回路について説明する。尚、本発明はかか
る変調回路に限定されるものでないことは勿論である
が、更に、アナログ通信方式及びデジタル通信方式の別
を問わず、本発明を適用できる。Next, referring to FIG. 3, π / 4 used in this embodiment will be described.
A modulation circuit of the shifted quadrature phase keying modulation method will be described. It should be noted that the present invention is not limited to such a modulation circuit, but the present invention can be applied irrespective of analog communication system or digital communication system.
入力端子（１）からのシリアルデジタル音声信号bm
が、直列／並列変換器（２）に供給されて、２ビットの
並列デジタル信号Xk,Ykに変換された後、差分位相エン
コーダ（３）に供給される。Serial digital audio signal bm from input terminal (1)
Is supplied to a serial / parallel converter (2) and converted into 2-bit parallel digital signals Xk and Yk, and then supplied to a differential phase encoder (3).
次に、第４図を参照して、この差分位相エンコーダ
（３）のエンコードについて説明する。第４図Ｉに示す
如く、Ｚ平面上の直交Ｉ軸（実軸）及びＯ軸（虚軸）座
標上の点Ａ（1,1）、Ｂ（−1,1）、Ｃ（−1,−１）及び
Ｄ（1,−１）を決める。又、第４図IIに示す如く、第４
図ＩのＺ平面上の直交Ｉ軸及びＯ軸座標を90゜（π/4）
回転せて得た直交Ｉ′軸（実軸）及びＱ′軸（虚軸）座
標上の点ａ（1,1）、ｂ（−1,1）、ｃ（−1,−１）及び
ｄ（1,−１）を決める。直交Ｉ′軸及びＱ′軸座標を平
行移動させて、両原点が一致するように、直交Ｉ軸及び
Ｑ軸座標に重ねる。かくすると、直交Ｉ′軸及びＱ′軸
座標上の点ａ、ｂ、ｃ及びｄの直交Ｉ軸及びＱ軸座標上
の各座標は、夫々 と成る。Next, the encoding of the differential phase encoder (3) will be described with reference to FIG. As shown in FIG. 4I, points A (1,1), B (−1,1), C (−1,1) on the orthogonal I axis (real axis) and O axis (imaginary axis) coordinates on the Z plane. -1) and D (1, -1) are determined. Also, as shown in FIG.
The orthogonal I-axis and O-axis coordinates on the Z plane of FIG.
Points a (1,1), b (−1,1), c (−1, −1) and d on orthogonal I ′ axis (real axis) and Q ′ axis (imaginary axis) coordinates obtained by rotation Determine (1, -1). The orthogonal I'-axis and Q'-axis coordinates are translated, and are superimposed on the orthogonal I-axis and Q-axis coordinates so that both origins coincide. Thus, the coordinates of the points a, b, c and d on the orthogonal I ′ axis and Q ′ axis coordinates on the orthogonal I axis and Q axis coordinates are respectively It becomes.
そして、エンコーダ（３）のエンコード出力Ik、Qk
は、直交Ｉ軸及びＱ軸座標上の点Ａ〜Ｄのいずれかの一
点から、直列／並列変換回路（２）の２ビットの出力X
k,Ykに応じた、点ａ〜ｄのいずれか一点への移動及び点
ａ〜ｄのいずれかの一点から、直列／並列変換回路
（２）の２ビットの出力Xk,Ykに応じた、点Ａ〜Ｄの何
れか一点への移動を示す。かかる点Ａ〜Ｄのいずれか一
点及び点ａ〜ｄのいずれか一点間の移動の様子を第３図
IIIに示し、かかる移動において、原点Ｏを通過するこ
とはない。Then, the encoded outputs Ik, Qk of the encoder (3)
Is a 2-bit output X of the serial / parallel conversion circuit (2) from one of points A to D on the orthogonal I-axis and Q-axis coordinates.
From the movement to any one of the points a to d according to k and Yk and from the one of the points a to d, according to the 2-bit output Xk and Yk of the serial / parallel conversion circuit (2), The movement to any one of the points A to D is shown. FIG. 3 shows the state of movement between any one of the points A to D and any one of the points a to d.
As shown in III, such a movement does not pass through the origin O.
そして、直交Ｉ軸及びＯ軸座標上の点Ａ〜Ｄのいずれ
か一点並びに点ａ〜ｄのいずれか一点間の移動は、その
各点と原点Ｏを結ぶ直線の角度の変化（差分）ΔΦで表
すことできる。The movement between any one of the points A to D and any one of the points a to d on the orthogonal I-axis and O-axis coordinates is caused by a change (difference) ΔΦ in the angle of a straight line connecting each point and the origin O. Can be represented by
そこで、Xk,YkとΔΦとの関係を、次に真理表にて示
す。Then, the relationship between Xk, Yk and ΔΦ is shown in the following truth table.
そして、Ik,Qkは、次式のように表される。 Then, Ik and Qk are represented by the following equations.
Ik＝Ik−１・cos〔ΔΦ（Xk,Yk）〕− Qk−１・sin〔ΔΦ（Xk,Yk）〕 Qk＝Ik−１・sin〔ΔΦ（Xk,Yk）〕＋ Qk−１・cos〔ΔΦ（Xk,Yk）〕 そして、エンコード出力Ik,Qkを夫々ベースバンドフ
ィルタ（4a）、（4b）を通じて、変調器（掛算器）（5
a）、（5b）に供給して、キャリア発振器（６）からの
キャリア及びそれを90゜移相器（７）によって90゜移相
させたキャリアを変調し（と掛算し）、その各出力を加
算器（８）で加算した後、被デジタル変調信号として出
力端子（９）から出力される。Ik = Ik− 1 · cos [ΔΦ (Xk, Yk)] − Qk− 1 · sin [ΔΦ (Xk, Yk)] Qk = Ik− 1 · sin [ΔΦ (Xk, Yk)] + Qk− 1 · cos [ΔΦ (Xk, Yk)] Then, the encode outputs Ik and Qk are passed through baseband filters (4a) and (4b), respectively, to a modulator (multiplier) (5
a) and (5b), which modulate (multiply with) the carrier from the carrier oscillator (6) and the carrier whose phase is shifted by 90 ° by the 90 ° phase shifter (7), and output each of them. Is added by the adder (8), and is output from the output terminal (9) as a digitally modulated signal.
上述せる本発明の等化方法によれば、入力端子からの
入力信号の１サンプリング周期に等しい遅延量を有する
初段乃至最終段の複数ｎ段の遅延手段と、入力信号及び
ｎ段の遅延手段の各出力信号に係数を乗算する（ｎ＋
１）個の係数乗算手段と、その（ｎ＋１）個の係数乗算
手段の出力を加算する加算手段と、その加算手段からの
出力等化信号に基づいて、その出力等化信号の振幅誤差
を推定する誤差推定手段と、その誤差推定手段からの判
定信号に基づいて、振幅誤差が最小となるような各別の
係数信号を形成して、（ｎ＋１）個の係数乗算手段にそ
れぞれ供給するタップゲイン調整手段と、初段の遅延手
段及び最終段の遅延手段からそれぞれはみ出した入力信
号のサンプリング信号をそれぞれ記憶する記憶手段とを
備える等化フィルタ手段を使用し、入力信号を構成する
連続するｍ個（但し、ｍ＞ｎ）のサンプリング信号を入
力端子に供給して、ｎ段の遅延手段を初段の遅延手段か
ら最終段の遅延手段に向かって正方向に伝送させて順次
遅延させ、その後、ｎ段の遅延手段を最終段の遅延手段
から初段の遅延手段に向かって逆方向に伝送させて順次
遅延させ、その後、ｎ段の遅延手段を初段の遅延手段か
ら最終段の遅延手段に向かって正方向に伝送させて順次
遅延させるようにするので、出力等化信号の振幅誤差を
補正することができると共に、入力信号の継続時間が短
ったり、入力信号にプリアンブルがなくても、等化出力
信号における、入力信号の当初の信号部分に対応する信
号部分の欠如の虞がなく成る。According to the equalization method of the present invention described above, a plurality of n-stage delay units of the first stage to the last stage having a delay amount equal to one sampling period of the input signal from the input terminal, and the input signal and the n-stage delay unit Multiply each output signal by a coefficient (n +
1) coefficient multiplying means, adding means for adding outputs of the (n + 1) coefficient multiplying means, and estimating an amplitude error of the output equalized signal based on an output equalized signal from the adding means. Error estimating means, and tap gains to be formed on the basis of the determination signal from the error estimating means to form respective coefficient signals each having a minimum amplitude error and to supply to (n + 1) coefficient multiplying means, respectively. Using an equalizing filter unit including an adjusting unit and a storage unit that stores a sampling signal of an input signal that protrudes from the first stage delay unit and the last stage delay unit, respectively, the input signal is composed of m continuous signals ( However, the sampling signal of m> n) is supplied to the input terminal, and the n-stage delay means are transmitted in the forward direction from the first-stage delay means to the last-stage delay means to be sequentially delayed, and thereafter, The n-stage delay means are transmitted in the reverse direction from the last-stage delay means to the first-stage delay means and are sequentially delayed, and thereafter, the n-stage delay means are transmitted from the first-stage delay means to the last-stage delay means. Since the signals are transmitted in the forward direction and sequentially delayed, the amplitude error of the output equalized signal can be corrected, and the equalization can be performed even if the duration of the input signal is short or the input signal has no preamble. There is no risk of the output signal lacking a signal portion corresponding to the original signal portion of the input signal.
第１図は本発明の実施例を示すブロック線図、第２図は
実施例の動作説明図、第３図は変調回路を示すブロック
線図、第４図はその変調回路のエンコードの説明図であ
る。 （12）は等化フィルタ部、D1、D2、・・・、Dmは夫々遅
延手段、M0、M1、M2、・・、Mmは夫々係数乗算手段、
A1、A2、・・・、Amは夫々加算手段、（14）は誤差推定
部、TGはタップゲイン調整部である。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of the embodiment, FIG. 3 is a block diagram showing a modulation circuit, and FIG. 4 is an explanatory diagram of encoding of the modulation circuit. It is. (12) is an equalizing filter unit, D 1 , D 2 ,..., Dm are delay means, M 0 , M 1 , M 2 ,.
A 1 , A 2 ,..., Am are addition means, (14) is an error estimator, and TG is a tap gain adjuster.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０４Ｌ 27/22 Ｈ０４Ｌ 27/22 Ｚ (56)参考文献 特開 平４−26215（ＪＰ，Ａ) 特開 昭63−142922（ＪＰ，Ａ) 特開 昭57−111135（ＪＰ，Ａ) 欧州公開458695（ＥＰ，Ａ１) (58)調査した分野(Int.Cl.6，ＤＢ名) H04B 3/00 - 3/18 H04B 7/005 H04L 27/00 - 27/22 H03H 15/00 - 17/00 ────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. 6 Identification symbol FI H04L27 / 22 H04L27 / 22Z (56) References JP-A-4-26215 (JP, A) JP-A-63-142922 ( JP, A) JP-A-57-111135 (JP, A) EP 458695 (EP, A1) (58) Fields investigated (Int. Cl. 6 , DB name) H04B 3/00-3/18 H04B 7 / 005 H04L 27/00-27/22 H03H 15/00-17/00
Claims (1)
周期に等しい遅延量を有する初段乃至最終段の複数ｎ段
の遅延手段と、上記入力信号及び上記ｎ段の遅延手段の
各出力信号に係数を乗算する（ｎ＋１）個の係数乗算手
段と、該（ｎ＋１）個の係数乗算手段の出力を加算する
加算手段と、該加算手段からの出力等化信号に基づい
て、該出力等化信号の振幅誤差を推定する誤差推定手段
と、該誤差推定手段からの判定信号に基づいて、上記振
幅誤差が最小となるような各別の係数信号を形成して、
上記（ｎ＋１）個の係数乗算手段にそれぞれ供給するタ
ップゲイン調整手段と、上記初段の遅延手段及び上記最
終段の遅延手段からそれぞれはみ出した上記入力信号の
サンプリング信号をそれぞれ記憶する記憶手段とを備え
る等化フィルタ手段を使用し、 上記入力信号を構成する連続するｍ個（但し、ｍ＞ｎ）
のサンプリング信号を上記入力端子に供給して、上記ｎ
段の遅延手段を上記初段の遅延手段から上記最終段の遅
延手段に向かって正方向に伝送させて順次遅延させ、そ
の後、上記ｎ段の遅延手段を上記最終段の遅延手段から
上記初段の遅延手段に向かって逆方向に伝送させて順次
遅延させ、その後、上記ｎ段の遅延手段を上記初段の遅
延手段から上記最終段の遅延手段に向かって正方向に伝
送させて順次遅延させるようにすることを特徴とする等
化方法。A plurality of n-stage delay means of a first stage to a last stage having a delay equal to one sampling period of an input signal from an input terminal; and a coefficient added to each of the input signal and each output signal of the n-stage delay means. (N + 1) coefficient multiplying means, an adding means for adding the outputs of the (n + 1) coefficient multiplying means, and an output equalized signal based on the output equalized signal from the adding means. Error estimating means for estimating the amplitude error, based on the determination signal from the error estimating means, to form each different coefficient signal such that the amplitude error is minimized,
Tap gain adjusting means for supplying the (n + 1) coefficient multiplying means to each; and memory means for storing sampling signals of the input signal which protrude from the first-stage delay means and the last-stage delay means, respectively. Using the equalization filter means, m consecutive (constituting m> n) composing the input signal
Is supplied to the input terminal, and the n
The delay means of the stage is transmitted in the forward direction from the delay means of the first stage toward the delay means of the last stage and is sequentially delayed, and then the delay means of the n stages is shifted from the delay means of the last stage to the delay of the first stage. The transmission is performed in the reverse direction toward the delay means and is sequentially delayed, and then the n-stage delay means is transmitted in the forward direction from the first-stage delay means to the final-stage delay means and is sequentially delayed. An equalization method characterized in that:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130752A JP2887501B2 (en) | 1990-05-21 | 1990-05-21 | Equalization method |
| US07/700,424 US5173924A (en) | 1990-05-21 | 1991-05-15 | Method for equalizing received burst signal |
| DE69112128T DE69112128T2 (en) | 1990-05-21 | 1991-05-21 | Method for equalizing a received burst signal. |
| EP91401310A EP0458695B1 (en) | 1990-05-21 | 1991-05-21 | Method for equalizing a received burst signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2130752A JP2887501B2 (en) | 1990-05-21 | 1990-05-21 | Equalization method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0426216A JPH0426216A (en) | 1992-01-29 |
| JP2887501B2 true JP2887501B2 (en) | 1999-04-26 |
Family
ID=15041797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2130752A Expired - Fee Related JP2887501B2 (en) | 1990-05-21 | 1990-05-21 | Equalization method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2887501B2 (en) |
-
1990
- 1990-05-21 JP JP2130752A patent/JP2887501B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0426216A (en) | 1992-01-29 |
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