JP2020025115A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2020025115A JP2020025115A JP2019192752A JP2019192752A JP2020025115A JP 2020025115 A JP2020025115 A JP 2020025115A JP 2019192752 A JP2019192752 A JP 2019192752A JP 2019192752 A JP2019192752 A JP 2019192752A JP 2020025115 A JP2020025115 A JP 2020025115A
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Abstract
Description
[1.半導体装置の構成]
以下、本実施の形態に係る半導体装置1の構成について説明する。本開示に係る半導体装置1は、半導体基板に2つの縦型MOS(Metal Oxide Semiconductor)トランジスタを形成した、フェイスダウン実装が可能なCSP(Chip Size Package:チップサイズパッケージ)型のマルチトランジスタチップである。上記2つの縦型MOSトランジスタは、パワートランジスタであり、いわゆる、トレンチMOS型FET(Field Effect Transistor)である。ただし、本実施の形態に係る半導体装置1は、固体撮像装置等のオプトエレクトロニクスに分類されるものには適用されない。
図1に示す半導体装置1において、例えば、第1導電型をN型、第2導電型をP型として、ソース領域14、ソース領域24、半導体基板32、および低濃度不純物層33はN型半導体であり、かつ、ボディ領域18およびボディ領域28はP型半導体であってもよい。
図3は、半導体装置1の、スマートホンやタブレットの充放電回路への応用例を示す回路図であり、半導体装置1は、制御IC2から与えられる制御信号に応じて、電池3から負荷4への放電動作および負荷4から電池3への充電動作を制御する。このようにスマートホンやタブレットの充放電回路として、半導体装置1が適用される場合、充電時間短縮や急速充電実現の制約から、オン抵抗は、20V耐圧仕様として、2.2〜2.4mΩ以下が求められる。
本実施の形態に係る半導体装置1において、Ni層はSi層よりも厚く、Si層は20μmよりも厚いことが望ましいことから、Ni層は、数十μmの厚さを有する層が必要となる。この観点から、Ni層は、例えば、湿式めっき法により形成される。湿式めっき法は、電気めっき法および化学めっき法に大別されるが、電気めっき法は膜厚の制限が少なく、低温形成が可能でありデバイスへの熱的影響が少ないという特徴を有する。よって、半導体装置1のNi層の製法として、電気めっき法が望ましい。Ni層の形成法として、蒸着等の乾式手法も挙げられるが、その結晶粒子は数十nmオーダーであり製膜レートが低いため、膜厚10μm以上を有する厚膜を製膜する手法としては非現実的である。
本実施の形態に係る半導体装置1は、さらに、金属層30(Ni層)の主面30bに形成された刻印を有する。上記刻印とは、例えば、製品名および製造日といった識別情報を含むマークである。半導体装置1では、フェイスダウン実装後であっても外部からの視認が容易となるように、主面30bに、例えば、レーザー照射により刻印される。上記レーザー照射に用いられるレーザーにはYAGレーザーが多く用いられており、YAGレーザーは樹脂材料を始め金属材料への微細な刻印が可能なレーザーである。
図13Aは、実施の形態に係る半導体装置1Aの断面図である。同図に示すように、半導体装置1Aは、半導体層40(Si層)と、金属層30(Ni層)および31(Ag層)と、トランジスタ10および20と、突起部36A、36B、37Aおよび37Bと、を有する。半導体装置1Aは、実施の形態に係る半導体装置1と比較して、突起部36A、36B、37Aおよび37Bを有する点、および、Si層を平面視した場合、Si層の外周がNi層およびAg層の外周よりも半導体装置1Aの中心方向に向かって後退している点が異なる。以下、半導体装置1Aについて、半導体装置1と同じ点については説明を省略し、異なる点を中心に説明する。
以上、本開示の1つまたは複数の態様に係る半導体装置について、実施の形態に基づいて説明したが、本開示は、この実施の形態に限定されるものではない。本開示の趣旨を逸脱しない限り、当業者が思いつく各種変形を本実施の形態に施したものや、異なる実施の形態における構成要素を組み合わせて構築される形態も、本開示の1つまたは複数の態様の範囲内に含まれてもよい。
2 制御IC
3 電池
4 負荷
10 トランジスタ(第1の縦型MOSトランジスタ)
11、11a、11A、11b、11B、11c、11d、21、21a、21A、21b、21B、21c、21d、111、121、211、221 ソース電極
12、13、22、23 部分
14、24 ソース領域
15、25、119、129、219、229 ゲート導体
16、26 ゲート絶縁膜
18、28 ボディ領域
19、19A、19B、29、29A、29B ゲート電極
20 トランジスタ(第2の縦型MOSトランジスタ)
30、31、130、131、230、231 金属層
30a、30b、31a、31b、40a、40b、50a、50b、51a、51b 主面
32 半導体基板
33 低濃度不純物層
34 層間絶縁層
35 パッシベーション層
36A、36B、37A、37B、38 突起部
39 合成物
40、140、150、240 半導体層
41、42、43A、43B、60 溝部
44 非晶質半導体
50、51 カバー層
70A、70C、70E 第1の層
70B、70D、70F 第2の層
132 基板
133、134、135、137、143、144、145、147 III族窒化物半導体層
136、146 2次元電子ガス
216 絶縁膜
232 SiC基板
233 低濃度n型不純物層
Claims (38)
- フェイスダウン実装が可能なチップサイズパッケージ型の半導体装置であって、
互いに背向する第1主面および第2主面を有し、シリコン、窒化ガリウムまたは炭化ケイ素からなる半導体層と、
互いに背向する第3主面および第4主面を有し、前記第3主面が前記第2主面に接触して形成され、前記半導体層よりも厚く、第1の金属材料からなる第1の金属層と、
互いに背向する第5主面および第6主面を有し、前記第5主面が前記第4主面に接触して形成され、前記半導体層よりも厚く、前記第1の金属材料よりもヤング率の大きい第2の金属材料からなる第2の金属層と、
前記半導体層の第1の領域に形成された第1の縦型電界効果トランジスタと、
前記半導体層において、前記第1の領域と前記第1主面に沿った方向で隣接する第2の領域に形成された第2の縦型電界効果トランジスタと、を有し、
前記第1の縦型電界効果トランジスタは前記半導体層の前記第1主面側に第1のソース電極および第1のゲート電極を有し、
前記第2の縦型電界効果トランジスタは前記半導体層の前記第1主面側に第2のソース電極および第2のゲート電極を有し、
前記第1の金属層は、前記第1の縦型電界効果トランジスタおよび前記第2の縦型電界効果トランジスタの共通ドレイン電極として機能し、
前記第1のソース電極から前記共通ドレイン電極を経由した前記第2のソース電極までの双方向経路を主電流経路とする
半導体装置。 - 前記第6主面の水平方向の凹凸周期は、前記第2の金属層を構成する結晶粒子の前記水平方向の結晶粒径よりも大きい
請求項1に記載の半導体装置。 - 前記第5主面における前記第2の金属層の結晶粒径は、前記第4主面における前記第1の金属層の結晶粒径より小さい
請求項1に記載の半導体装置。 - 前記第2の金属材料の線膨張係数は、前記第1の金属材料の線膨張係数より小さい
請求項1に記載の半導体装置。 - 前記第2の金属層の厚さは30μm以下である
請求項1に記載の半導体装置。 - 前記第2の金属層は、
前記第5主面を有する第1の層と、
前記第6主面を有する第2の層とを含み、
前記第1の層の結晶粒径よりも前記第2の層の結晶粒径が大きい
請求項1に記載の半導体装置。 - 前記第2の金属層は、
前記第5主面を有する第1の層と、
前記第6主面を有する第2の層とを含み、
前記第1の層の結晶粒径よりも前記第2の層の結晶粒径が小さい
請求項1に記載の半導体装置。 - 前記第2の金属層は、
前記第5主面を有する第1の層と、
前記第6主面を有する第2の層とを含み、
前記第1の層の結晶粒径と前記第2の層の結晶粒径とは略同じであり、かつ、前記第2の金属層の結晶粒径は、前記第1の金属層の結晶粒径より小さい
請求項1に記載の半導体装置。 - 前記第2の金属層は、
前記第5主面を有する第1の層と、
前記第6主面を有する第2の層とを含み、
前記第6主面の水平方向において、前記第1の層を構成する金属結晶と前記第2の層を構成する金属結晶とは、優先配向面が異なる
請求項1に記載の半導体装置。 - 前記第6主面の水平方向において、
前記第1の層および前記第2の層の一方を構成する金属結晶は、{100}面優先配向しており、
前記第1の層および前記第2の層の他方を構成する金属結晶は、{110}面優先配向している
請求項9に記載の半導体装置。 - 前記第2の金属層を構成する金属結晶は、前記第6主面において{100}面優先配向している
請求項1に記載の半導体装置。 - 前記第2の金属層を構成する金属結晶は、前記第6主面において{110}面優先配向している
請求項1に記載の半導体装置。 - さらに、
前記第2の金属層の前記第6主面に形成された刻印を有し、
前記刻印のパターン幅は、前記第6主面の水平方向の凹凸周期より大きい
請求項1に記載の半導体装置。 - 前記刻印のパターン深さは、前記第6主面の凹凸の最大高さ粗さより大きい
請求項13に記載の半導体装置。 - さらに、
前記第2の金属層を平面視した場合の前記第2の金属層の外周に、前記第5主面から前記第6主面に向かう方向に、前記第6主面から突出した第1突起部を有し、
前記第1突起部は、前記第1の金属材料および前記第2の金属材料の少なくとも一方を含む
請求項1に記載の半導体装置。 - 前記第1突起部は、前記平面視における前記第2の金属層の外周の対向する2辺に形成されている
請求項15に記載の半導体装置。 - 前記第1突起部の突出高さは、前記第2の金属層の厚さの1/3以上である
請求項15に記載の半導体装置。 - 前記第1突起部の突出幅は、4μm以上である
請求項15に記載の半導体装置。 - 前記第1突起部における前記第2の金属材料の含有量は、前記第1突起部における前記第1の金属材料の含有量よりも多い
請求項15に記載の半導体装置。 - 前記半導体層を平面視した場合に、前記半導体層の外周は前記第1の金属層の外周から間隔を空けて内側に形成され、
さらに、
前記第1の金属層を平面視した場合の前記第1の金属層の外周に、前記第4主面から前記第3主面に向かう方向に、前記第3主面から突出した第2突起部を有し、
前記第2突起部は、前記第1の金属材料および前記第2の金属材料の少なくとも一方を含む
請求項1に記載の半導体装置。 - 前記第2突起部は、前記平面視における前記第1の金属層の外周の対向する2辺に形成されている
請求項20に記載の半導体装置。 - さらに、
前記第1の金属層および前記第2の金属層の少なくとも一方の外周側面には、前記第1の金属層を平面視した場合の前記第1の金属層の中央から前記第1の金属層の外周に向かう方向に、第3突起部を有する
請求項1に記載の半導体装置。 - さらに、
互いに背向する第7主面および第8主面を有し、前記第7主面が前記第6主面に接触して形成され、セラミック材料またはプラスチック材料からなる第1のカバー層を有する
請求項1に記載の半導体装置。 - さらに、
前記第1の金属層を平面視した場合の前記第1の金属層の外縁部に、互いに背向する第9主面および第10主面を有し、前記第10主面が前記第3主面に接触して形成され、セラミック材料またはプラスチック材料からなる第2のカバー層を有する
請求項1に記載の半導体装置。 - 前記半導体層の外縁部であって前記半導体層の外周辺に沿って形成された、前記第3主面を底面とする溝部を有する
請求項24に記載の半導体装置。 - さらに、
前記第1の金属層および前記第2の金属層の少なくとも一方の外周側面には、前記第1の金属材料と前記第2の金属材料との合成物が形成されている
請求項1に記載の半導体装置。 - 前記合成物は、前記第1の金属層および前記第2の金属層を平面視した場合における前記半導体装置の全周に渡り、前記外周側面に形成されている
請求項26に記載の半導体装置。 - 前記第3主面から前記第6主面に向かう方向において、前記合成物の中心位置は、前記第3主面から前記第6主面までの距離の半分の位置と前記第6主面の位置との間である
請求項26に記載の半導体装置。 - 前記半導体層を平面視した場合において、前記半導体層の外周は前記第1の金属層の外周から間隔を空けて内側に形成されている
請求項1に記載の半導体装置。 - 前記平面視において、前記半導体層の外周は、全周に渡り前記第1の金属層の外周から間隔を空けて内側に形成されている
請求項29に記載の半導体装置。 - 前記間隔の長さは、15μm以上である
請求項29に記載の半導体装置。 - 前記半導体層の外周側面のうちの前記第3主面と接する前記第2主面側の端部側面の凹凸の最大高さ粗さは、前記半導体層の外周側面のうちの前記第1主面側の側面の凹凸の最大高さ粗さと、略等しい
請求項29に記載の半導体装置。 - 前記半導体層の外周側面は、鋭角な頂点を含む凹凸形状を有している
請求項29に記載の半導体装置。 - 前記半導体層の外周側面は、非晶質半導体で覆われている
請求項29に記載の半導体装置。 - 前記半導体層は、前記第2主面側に形成され、シリコンからなる半導体基板と、
前記第1主面側に形成され、前記半導体基板に含まれる第1導電型不純物の濃度より低い濃度の前記第1導電型不純物を含む低濃度不純物層とを有し、
前記第1の縦型電界効果トランジスタは、前記半導体層の表面に第1のゲート導体を含む固体部材が充填された第1の複数の溝部を有し、
前記第2の縦型電界効果トランジスタは、前記半導体層の表面に第2のゲート導体を含む固体部材が充填された第2の複数の溝部を有し、
前記半導体装置は、さらに、
前記半導体層の外縁部表面であって前記半導体層の外周辺に沿って形成された、シリコンを含む固体部材が充填された第3の複数の溝部を有する
請求項1に記載の半導体装置。 - 前記第1の複数の溝部と前記第3の複数の溝部との間隔、および、前記第2の複数の溝部と前記第3の複数の溝部との間隔は、前記第1の複数の溝部の隣り合う溝部の間隔よりも大きく、かつ、前記第2の複数の溝部の隣り合う溝部の間隔よりも大きい
請求項35に記載の半導体装置。 - さらに、
前記第1のソース電極または前記第2のソース電極と一部重なるように形成された保護層を有し、
前記半導体層を平面視した場合に、前記保護層の外周は、前記半導体層の外周から間隔を空けて内側に形成されており、
前記第3の複数の溝部は、前記平面視において、前記半導体層の外周から前記保護層の外周まで形成されている
請求項35に記載の半導体装置。 - 前記第3の複数の溝部における溝部のピッチは、前記第1の複数の溝部における溝部のピッチ、および、前記第2の複数の溝部における溝部のピッチと同じである
請求項35に記載の半導体装置。
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WO2024042809A1 (ja) * | 2022-08-24 | 2024-02-29 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
JP7507322B1 (ja) | 2022-08-24 | 2024-06-27 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
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CN108598161B (zh) * | 2018-04-29 | 2021-03-09 | 杭州电子科技大学 | 一种利用全固态电池实现的增强型iii-v hemt器件 |
KR102234945B1 (ko) * | 2018-06-19 | 2021-04-01 | 누보톤 테크놀로지 재팬 가부시키가이샤 | 반도체 장치 |
JP6775872B1 (ja) * | 2018-12-19 | 2020-10-28 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
JP7509711B2 (ja) * | 2021-03-23 | 2024-07-02 | 株式会社東芝 | 半導体装置 |
CN116646351B (zh) * | 2021-03-29 | 2024-02-09 | 新唐科技日本株式会社 | 半导体装置、电池保护电路及电源管理电路 |
WO2023139813A1 (ja) * | 2022-01-19 | 2023-07-27 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置及びレーザマーキング方法 |
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JP7507322B1 (ja) | 2022-08-24 | 2024-06-27 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置 |
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WO2019244383A1 (ja) | 2019-12-26 |
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