JP2018519581A - メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え - Google Patents
メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え Download PDFInfo
- Publication number
- JP2018519581A JP2018519581A JP2017560966A JP2017560966A JP2018519581A JP 2018519581 A JP2018519581 A JP 2018519581A JP 2017560966 A JP2017560966 A JP 2017560966A JP 2017560966 A JP2017560966 A JP 2017560966A JP 2018519581 A JP2018519581 A JP 2018519581A
- Authority
- JP
- Japan
- Prior art keywords
- translation
- address translation
- requests
- address
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/50—Control mechanisms for virtual memory, cache or TLB
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/655—Same page detection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/682—Multiprocessor TLB consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/683—Invalidation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/684—TLB miss handling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
本特許出願は、本出願の譲受人に譲渡され、参照により本明細書に明確に組み込まれる、2015年5月29日に出願された"MULTI-THREADED TRANSLATION AND TRANSACTION RE-ORDERING FOR MEMORY MANAGEMENT UNITS"と題する米国仮出願第62/168,712号の優先権を主張する。
104 MMU
106 システムメモリ
108 変換キャッシュ
110 トランザクションキュー
112 エントリTTW0
114 変換テーブルウォーカ(TTW)
116 クライアント入力トランザクション
120 バス
122 応答
124 バス
200 処理システム
202 アップストリームデバイス
204 MMU
206 システムメモリ
208 変換キャッシュ
209 変換要求
210 1次スケジューラ
211 変換結果
212a〜212n TTW
214 TTW
216 クライアント入力トランザクション
220 2次スケジューラ
222 プリフェッチエンジン
224 事前フィルタ/事前フィルタ処理ブロック
226 事後フィルタ/事後フィルタ処理ブロック
228 変換要求
230 変換要求
232 変換結果
234 変換結果
236 変換要求
238 変換結果
240 変換結果
242 クライアント出力トランザクション
244 応答
302 アービトレーションユニット
304a スロット
304n スロット
308 メモリ変換スケジューリング
402 アービトレーションブロック
404a スロット
404m スロット
406 スケジューリングブロック
500 処理システム
504 MMU
509 変換要求
510 メインスケジューラ
511 変換結果
524 事前フィルタ処理ブロック
526 事後フィルタ処理ブロック
528 要求
536 変換要求
602 変換テーブルアクセスフィルタ
606 TTW要求状態/TTW要求状態ブロック
608 変換結果キャッシュ
612a レジスタ、記憶手段
612n レジスタ、記憶手段
702a ページL1
702b ページL2
704 テーブル
706 テーブル
1100 ワイヤレスデバイス
1126 ディスプレイコントローラ
1128 ディスプレイ
1130 入力デバイス
1134 コーダ/デコーダ(コーデック)
1136 スピーカ
1138 マイクロフォン
1140 ワイヤレスコントローラ
1144 電源
Claims (51)
前記マルチスレッドMMUが、システムメモリの対応する変換されたアドレスを取得するために、前記2つ以上のアドレス変換要求のうちの少なくとも2つを並列に処理するようにさらに構成される、装置。
2つ以上のアドレス変換要求を受信するステップと、
マルチスレッドメモリ管理ユニット(MMU)内で、システムメモリの対応する変換されたアドレスを取得するために前記2つ以上のアドレス変換要求に対する2つ以上のアドレス変換を並列に実行するステップと
を含む、方法。
記憶するための手段の対応する変換されたアドレスを取得するために、前記2つ以上のアドレス変換要求に対する2つ以上のアドレス変換を実行するための手段と
を含む、装置。
2つ以上のアドレス変換要求を受信するためのコードと、
システムメモリの対応する変換されたアドレスを取得するために、前記2つ以上のアドレス変換要求に対する2つ以上のアドレス変換を並列に実行するためのコードと
を含む、非一時的コンピュータ可読記憶媒体。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562168712P | 2015-05-29 | 2015-05-29 | |
US62/168,712 | 2015-05-29 | ||
US14/859,351 US10007619B2 (en) | 2015-05-29 | 2015-09-20 | Multi-threaded translation and transaction re-ordering for memory management units |
US14/859,351 | 2015-09-20 | ||
PCT/US2016/029502 WO2016195850A1 (en) | 2015-05-29 | 2016-04-27 | Multi-threaded translation and transaction re-ordering for memory management units |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018519581A true JP2018519581A (ja) | 2018-07-19 |
JP2018519581A5 JP2018519581A5 (ja) | 2018-09-06 |
Family
ID=57397568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017560966A Ceased JP2018519581A (ja) | 2015-05-29 | 2016-04-27 | メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え |
Country Status (9)
Country | Link |
---|---|
US (1) | US10007619B2 (ja) |
EP (1) | EP3304320A1 (ja) |
JP (1) | JP2018519581A (ja) |
KR (1) | KR20180013924A (ja) |
CN (1) | CN107710173A (ja) |
BR (1) | BR112017025625A2 (ja) |
CA (1) | CA2983797A1 (ja) |
TW (1) | TW201710908A (ja) |
WO (1) | WO2016195850A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9830224B2 (en) * | 2013-03-15 | 2017-11-28 | Nvidia Corporation | Selective fault stalling for a GPU memory pipeline in a unified virtual memory system |
US10509729B2 (en) | 2016-01-13 | 2019-12-17 | Intel Corporation | Address translation for scalable virtualization of input/output devices |
US10228981B2 (en) | 2017-05-02 | 2019-03-12 | Intel Corporation | High-performance input-output devices supporting scalable virtualization |
US10635654B2 (en) * | 2017-06-12 | 2020-04-28 | Samsung Electronics Co., Ltd. | Data journaling for large solid state storage devices with low DRAM/SRAM |
US10649912B2 (en) * | 2017-07-14 | 2020-05-12 | International Business Machines Corporation | Method and apparatus for an efficient TLB lookup |
US20190087351A1 (en) * | 2017-09-20 | 2019-03-21 | Qualcomm Incorporated | Transaction dispatcher for memory management unit |
US10628072B2 (en) * | 2018-08-21 | 2020-04-21 | Samsung Electronics Co., Ltd. | Scalable architecture enabling large memory system for in-memory computations |
GB2578099B (en) | 2018-10-15 | 2021-05-12 | Advanced Risc Mach Ltd | Memory access control |
US11636043B2 (en) | 2021-08-30 | 2023-04-25 | International Business Machines Corporation | Sleeping and waking-up address translation that conflicts with translation level of active page table walks |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009026320A (ja) * | 2003-07-25 | 2009-02-05 | Rmi Corp | プロセッサ |
US20100106921A1 (en) * | 2006-11-01 | 2010-04-29 | Nvidia Corporation | System and method for concurrently managing memory access requests |
US20120159039A1 (en) * | 2010-12-16 | 2012-06-21 | Andy Kegel | Generalized Control Registers |
US20130031332A1 (en) * | 2011-07-26 | 2013-01-31 | Bryant Christopher D | Multi-core shared page miss handler |
JP2013509655A (ja) * | 2009-10-29 | 2013-03-14 | アップル インコーポレイテッド | 複数の仮想キューを含むアドレス変換ユニット |
US20140075123A1 (en) * | 2012-09-13 | 2014-03-13 | Gur Hildesheim | Concurrent Control For A Page Miss Handler |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010052053A1 (en) | 2000-02-08 | 2001-12-13 | Mario Nemirovsky | Stream processing unit for a multi-streaming processor |
EP1182571B1 (en) * | 2000-08-21 | 2011-01-26 | Texas Instruments Incorporated | TLB operations based on shared bit |
US7434000B1 (en) | 2004-06-30 | 2008-10-07 | Sun Microsystems, Inc. | Handling duplicate cache misses in a multithreaded/multi-core processor |
US7814253B2 (en) * | 2007-04-16 | 2010-10-12 | Nvidia Corporation | Resource arbiter |
US7904692B2 (en) * | 2007-11-01 | 2011-03-08 | Shrijeet Mukherjee | Iommu with translation request management and methods for managing translation requests |
US8271700B1 (en) * | 2007-11-23 | 2012-09-18 | Pmc-Sierra Us, Inc. | Logical address direct memory access with multiple concurrent physical ports and internal switching |
US8108584B2 (en) * | 2008-10-15 | 2012-01-31 | Intel Corporation | Use of completer knowledge of memory region ordering requirements to modify transaction attributes |
EP2441005A2 (en) | 2009-06-09 | 2012-04-18 | Martin Vorbach | System and method for a cache in a multi-core processor |
US8301865B2 (en) | 2009-06-29 | 2012-10-30 | Oracle America, Inc. | System and method to manage address translation requests |
US8738860B1 (en) | 2010-10-25 | 2014-05-27 | Tilera Corporation | Computing in parallel processing environments |
US8954986B2 (en) * | 2010-12-17 | 2015-02-10 | Intel Corporation | Systems and methods for data-parallel processing |
US8695008B2 (en) * | 2011-04-05 | 2014-04-08 | Qualcomm Incorporated | Method and system for dynamically controlling power to multiple cores in a multicore processor of a portable computing device |
US9411728B2 (en) * | 2011-12-23 | 2016-08-09 | Intel Corporation | Methods and apparatus for efficient communication between caches in hierarchical caching design |
CN102763086A (zh) * | 2012-01-18 | 2012-10-31 | 华为技术有限公司 | 分布式计算任务处理***和任务处理方法 |
US9152566B2 (en) * | 2012-06-15 | 2015-10-06 | International Business Machines Corporation | Prefetch address translation using prefetch buffer based on availability of address translation logic |
US10037228B2 (en) * | 2012-10-25 | 2018-07-31 | Nvidia Corporation | Efficient memory virtualization in multi-threaded processing units |
US20150100733A1 (en) | 2013-10-03 | 2015-04-09 | Synopsys, Inc. | Efficient Memory Organization |
US9411745B2 (en) | 2013-10-04 | 2016-08-09 | Qualcomm Incorporated | Multi-core heterogeneous system translation lookaside buffer coherency |
CN104484228B (zh) * | 2014-12-30 | 2017-12-29 | 成都因纳伟盛科技股份有限公司 | 基于Intelli‑DSC的分布式并行任务处理*** |
US20160210069A1 (en) * | 2015-01-21 | 2016-07-21 | Bitdefender IPR Management Ltd. | Systems and Methods For Overriding Memory Access Permissions In A Virtual Machine |
US10019380B2 (en) * | 2015-09-25 | 2018-07-10 | Qualcomm Incorporated | Providing memory management functionality using aggregated memory management units (MMUs) |
-
2015
- 2015-09-20 US US14/859,351 patent/US10007619B2/en active Active
-
2016
- 2016-04-27 CA CA2983797A patent/CA2983797A1/en not_active Abandoned
- 2016-04-27 WO PCT/US2016/029502 patent/WO2016195850A1/en active Search and Examination
- 2016-04-27 EP EP16720680.4A patent/EP3304320A1/en not_active Withdrawn
- 2016-04-27 JP JP2017560966A patent/JP2018519581A/ja not_active Ceased
- 2016-04-27 KR KR1020177034178A patent/KR20180013924A/ko not_active Application Discontinuation
- 2016-04-27 CN CN201680029881.7A patent/CN107710173A/zh active Pending
- 2016-04-27 BR BR112017025625A patent/BR112017025625A2/pt not_active Application Discontinuation
- 2016-05-20 TW TW105115829A patent/TW201710908A/zh unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009026320A (ja) * | 2003-07-25 | 2009-02-05 | Rmi Corp | プロセッサ |
US20100106921A1 (en) * | 2006-11-01 | 2010-04-29 | Nvidia Corporation | System and method for concurrently managing memory access requests |
JP2013509655A (ja) * | 2009-10-29 | 2013-03-14 | アップル インコーポレイテッド | 複数の仮想キューを含むアドレス変換ユニット |
US20120159039A1 (en) * | 2010-12-16 | 2012-06-21 | Andy Kegel | Generalized Control Registers |
US20130031332A1 (en) * | 2011-07-26 | 2013-01-31 | Bryant Christopher D | Multi-core shared page miss handler |
US20140075123A1 (en) * | 2012-09-13 | 2014-03-13 | Gur Hildesheim | Concurrent Control For A Page Miss Handler |
Also Published As
Publication number | Publication date |
---|---|
US10007619B2 (en) | 2018-06-26 |
WO2016195850A1 (en) | 2016-12-08 |
KR20180013924A (ko) | 2018-02-07 |
BR112017025625A2 (pt) | 2018-08-07 |
CN107710173A (zh) | 2018-02-16 |
EP3304320A1 (en) | 2018-04-11 |
US20160350234A1 (en) | 2016-12-01 |
CA2983797A1 (en) | 2016-12-08 |
TW201710908A (zh) | 2017-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10007619B2 (en) | Multi-threaded translation and transaction re-ordering for memory management units | |
US20200363967A1 (en) | On-chip Atomic Transaction Engine | |
US8683140B2 (en) | Cache-based speculation of stores following synchronizing operations | |
US9639466B2 (en) | Control mechanism for fine-tuned cache to backing-store synchronization | |
US8180981B2 (en) | Cache coherent support for flash in a memory hierarchy | |
US9201796B2 (en) | System cache with speculative read engine | |
US11635961B2 (en) | Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file | |
CN100351781C (zh) | 多线程并行处理器结构中所用的微引擎的存储器引用指令 | |
US20080162760A1 (en) | Efficient resource arbitration | |
JP5059609B2 (ja) | メモリへの様々なタイプのアクセスを予測するため、およびキャッシュメモリに関連付けられた予測を管理するための、システム、装置、および方法 | |
US9135177B2 (en) | Scheme to escalate requests with address conflicts | |
US11321248B2 (en) | Multiple-requestor memory access pipeline and arbiter | |
KR20150107831A (ko) | 데이터 버퍼와 연관된 스누프 필터링의 제공 | |
US9378144B2 (en) | Modification of prefetch depth based on high latency event | |
US10331357B2 (en) | Tracking stores and loads by bypassing load store units | |
US20130054896A1 (en) | System memory controller having a cache | |
US9286068B2 (en) | Efficient usage of a multi-level register file utilizing a register file bypass | |
US8458406B2 (en) | Multiple critical word bypassing in a memory controller | |
US20230080128A1 (en) | Complex I/O Value Prediction for Multiple Values with Physical or Virtual Addresses | |
US20070156960A1 (en) | Ordered combination of uncacheable writes | |
CN117940908A (zh) | 动态分配高速缓存存储器作为ram | |
GB2502858A (en) | A method of copying data from a first memory location and storing it in a cache line associated with a different memory location | |
CN113849263A (zh) | 用于启用对工作提交的细粒度的服务质量或速率控制的***、装置和方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180724 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180724 |
|
A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20180724 |
|
A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20180801 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20181130 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20181210 |
|
A045 | Written measure of dismissal of application [lapsed due to lack of payment] |
Free format text: JAPANESE INTERMEDIATE CODE: A045 Effective date: 20190422 |