JP2016225474A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP2016225474A JP2016225474A JP2015110789A JP2015110789A JP2016225474A JP 2016225474 A JP2016225474 A JP 2016225474A JP 2015110789 A JP2015110789 A JP 2015110789A JP 2015110789 A JP2015110789 A JP 2015110789A JP 2016225474 A JP2016225474 A JP 2016225474A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor substrate
- insulating film
- hole
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 67
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 137
- 230000004888 barrier function Effects 0.000 description 23
- 229910052581 Si3N4 Inorganic materials 0.000 description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 18
- 239000000463 material Substances 0.000 description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 6
- 239000012044 organic layer Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910007637 SnAg Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
Abstract
【解決手段】実施形態にかかる半導体装置1は、貫通孔180Hが設けられた半導体基板11と、下層配線122を含むデバイス層12と、デバイス層12を覆う絶縁層13と、絶縁層13を貫通する第1貫通電極14と、半導体基板11の貫通孔180Hの開口径と実質的に同じかもしくは大きな径の開口が設けられた第1絶縁膜171/172と、第1絶縁膜171/172上から半導体基板11の貫通孔180Hの内側面に位置する第2絶縁膜173と、第2絶縁膜173上から半導体基板11の貫通孔180H内を経てデバイス層12中の下層配線122と電気的に接続する第2貫通電極18とを備えてもよい。
【選択図】図1
Description
Claims (6)
- 第1面に配線を含むデバイス層と前記デバイス層を覆う絶縁層と前記絶縁層を貫通する第1貫通電極とが形成された半導体基板における前記第1面とは反対側の第2面上に、第1絶縁膜を形成する工程と、
前記第1絶縁膜が形成された前記半導体基板を前記第2面側から異方性ドライエッチングにより彫り込むことで前記デバイス層を露出させる貫通孔を形成する工程と、
前記貫通孔の開口端部分の前記第1絶縁膜をエッチングにより除去する工程と、
前記第1絶縁膜上と前記貫通孔の内側面および底面とに第2絶縁膜を形成する工程と、
前記貫通孔の前記底面に形成された前記第2絶縁膜および前記デバイス層における第3絶縁膜を除去することで前記デバイス層の前記配線を露出させる工程と、
前記第2絶縁膜上から前記貫通孔内を経て前記デバイス層中の前記配線と電気的に接続する第2貫通電極を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1絶縁膜は、前記半導体基板の前記第2面上に位置するシリコン酸化膜を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2貫通電極は、
前記第2絶縁膜上から前記貫通孔内側面を経て前記デバイス層中の前記配線と接触する第1メタル層と、
前記第1メタル層上に形成された第2メタル層と、
前記第2メタル層上に形成された第3メタル層と、
を含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記半導体基板の厚さ方向において前記前記第1絶縁膜とオーバラップする領域が残るように前記1メタル層と前記第2メタル層とをパターニングする工程をさらに含むことを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1絶縁膜を形成する前に前記半導体基板を50マイクロメートル以下に薄厚化する工程をさらに含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 第1面から前記第1面とは反対側の第2面まで貫通する貫通孔が設けられた半導体基板と、
前記半導体基板の前記第1面に位置し、配線を含むデバイス層と、
前記デバイス層を覆う絶縁層と、
前記絶縁層を貫通する第1貫通電極と、
前記半導体基板の前記第2面上に位置し、前記半導体基板の前記貫通孔の開口径と実質的に同じかもしくは大きな径の開口が設けられた第1絶縁膜と、
前記第1絶縁膜上から前記半導体基板の前記貫通孔の内側面に位置する第2絶縁膜と、
前記第2絶縁膜上から前記半導体基板の前記貫通孔内を経て前記デバイス層中の前記配線と電気的に接続する第2貫通電極と、
を備えることを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015110789A JP6479578B2 (ja) | 2015-05-29 | 2015-05-29 | 半導体装置の製造方法および半導体装置 |
TW104139211A TWI579968B (zh) | 2015-05-29 | 2015-11-25 | 半導體裝置之製造方法及半導體裝置 |
CN201510848888.9A CN106206416B (zh) | 2015-05-29 | 2015-11-27 | 半导体装置的制造方法以及半导体装置 |
US15/061,659 US10204862B2 (en) | 2015-05-29 | 2016-03-04 | Method of manufacturing semiconductor device, and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015110789A JP6479578B2 (ja) | 2015-05-29 | 2015-05-29 | 半導体装置の製造方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016225474A true JP2016225474A (ja) | 2016-12-28 |
JP6479578B2 JP6479578B2 (ja) | 2019-03-06 |
Family
ID=57399093
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015110789A Active JP6479578B2 (ja) | 2015-05-29 | 2015-05-29 | 半導体装置の製造方法および半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10204862B2 (ja) |
JP (1) | JP6479578B2 (ja) |
CN (1) | CN106206416B (ja) |
TW (1) | TWI579968B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018170363A (ja) * | 2017-03-29 | 2018-11-01 | 東芝メモリ株式会社 | 半導体装置の製造方法及び半導体装置 |
US11043419B2 (en) | 2018-09-05 | 2021-06-22 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6697411B2 (ja) * | 2017-03-29 | 2020-05-20 | キオクシア株式会社 | 半導体装置の製造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006032695A (ja) * | 2004-07-16 | 2006-02-02 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2009158862A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体パッケージ |
JP2010232661A (ja) * | 2009-03-27 | 2010-10-14 | Taiwan Semiconductor Manufacturing Co Ltd | ビア構造とそれを形成するビアエッチングプロセス |
JP2013520830A (ja) * | 2010-02-25 | 2013-06-06 | エスピーティーエス テクノロジーズ リミティド | ビア及びエッチングされた構造におけるコンフォーマル絶縁層の形成方法及びパターン形成方法 |
JP2014011309A (ja) * | 2012-06-29 | 2014-01-20 | Ps4 Luxco S A R L | 半導体装置およびその製造方法 |
JP2015002299A (ja) * | 2013-06-17 | 2015-01-05 | 株式会社ザイキューブ | 漏斗状の貫通電極およびその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5656341B2 (ja) * | 2007-10-29 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置およびその製造方法 |
JP2012142414A (ja) | 2010-12-28 | 2012-07-26 | Panasonic Corp | 半導体装置及びその製造方法並びにそれを用いた積層型半導体装置 |
JP2012231096A (ja) | 2011-04-27 | 2012-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2015041691A (ja) | 2013-08-21 | 2015-03-02 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
-
2015
- 2015-05-29 JP JP2015110789A patent/JP6479578B2/ja active Active
- 2015-11-25 TW TW104139211A patent/TWI579968B/zh active
- 2015-11-27 CN CN201510848888.9A patent/CN106206416B/zh active Active
-
2016
- 2016-03-04 US US15/061,659 patent/US10204862B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006032695A (ja) * | 2004-07-16 | 2006-02-02 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2009158862A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体パッケージ |
JP2010232661A (ja) * | 2009-03-27 | 2010-10-14 | Taiwan Semiconductor Manufacturing Co Ltd | ビア構造とそれを形成するビアエッチングプロセス |
JP2013520830A (ja) * | 2010-02-25 | 2013-06-06 | エスピーティーエス テクノロジーズ リミティド | ビア及びエッチングされた構造におけるコンフォーマル絶縁層の形成方法及びパターン形成方法 |
JP2014011309A (ja) * | 2012-06-29 | 2014-01-20 | Ps4 Luxco S A R L | 半導体装置およびその製造方法 |
JP2015002299A (ja) * | 2013-06-17 | 2015-01-05 | 株式会社ザイキューブ | 漏斗状の貫通電極およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018170363A (ja) * | 2017-03-29 | 2018-11-01 | 東芝メモリ株式会社 | 半導体装置の製造方法及び半導体装置 |
US11043419B2 (en) | 2018-09-05 | 2021-06-22 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP6479578B2 (ja) | 2019-03-06 |
TW201642391A (zh) | 2016-12-01 |
US10204862B2 (en) | 2019-02-12 |
US20160351503A1 (en) | 2016-12-01 |
CN106206416A (zh) | 2016-12-07 |
TWI579968B (zh) | 2017-04-21 |
CN106206416B (zh) | 2019-05-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI600116B (zh) | 半導體裝置及半導體裝置之製造方法 | |
JP4787559B2 (ja) | 半導体装置およびその製造方法 | |
TWI429046B (zh) | 半導體裝置及其製造方法 | |
JP6502751B2 (ja) | 半導体装置および半導体装置の製造方法 | |
WO2010035377A1 (ja) | 半導体装置及びその製造方法 | |
WO2010035379A1 (ja) | 半導体装置及びその製造方法 | |
TW201023331A (en) | Semiconductor device and method for forming the same | |
CN110880487B (zh) | 半导体装置及其制造方法 | |
WO2010035375A1 (ja) | 半導体装置及びその製造方法 | |
TWI684242B (zh) | 半導體裝置之製造方法及半導體裝置 | |
TWI708343B (zh) | 半導體裝置及其製造方法 | |
JP6479578B2 (ja) | 半導体装置の製造方法および半導体装置 | |
JP2019204894A (ja) | 半導体装置の製造方法および半導体装置 | |
JP5377657B2 (ja) | 半導体装置の製造方法 | |
JP5834563B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20170605 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170804 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180427 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180508 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180704 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20180905 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190108 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190206 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6479578 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |