JP2007104741A - Control circuit for step-up/down converter - Google Patents

Control circuit for step-up/down converter Download PDF

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JP2007104741A
JP2007104741A JP2005287449A JP2005287449A JP2007104741A JP 2007104741 A JP2007104741 A JP 2007104741A JP 2005287449 A JP2005287449 A JP 2005287449A JP 2005287449 A JP2005287449 A JP 2005287449A JP 2007104741 A JP2007104741 A JP 2007104741A
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signal
error
control circuit
circuit
error signal
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Takuya Ishii
卓也 石井
Hiroki Akashi
裕樹 明石
Makoto Ishimaru
誠 石丸
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters

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  • Dc-Dc Converters (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a control circuit for operating a step-up/down converter stably. <P>SOLUTION: The control circuit 10A for a step-up/down converter comprises an error amplifier circuit 11 generating a first error signal based on the error between the output voltage from the step-up/down converter and a target value, an inverting amplifier circuit 12 generating a second error signal by inverting the first error signal centering on a reference potential, an oscillator 13 generating a ramp signal centering on the reference potential, a first comparator 14 for comparing the first error signal with the ramp signal, a second comparator 15 for comparing the second error signal with the ramp signal, a step-up control circuit 16 for controlling the operation of a step-up circuit in the step-up/down converter based on AND of the output from the first comparator and the output from the second comparator, and a step-down control circuit 17 for controlling the operation of a step-down circuit in the step-up/down converter based on OR of the output from the first comparator and the output from the second comparator. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、直流の入力電圧を所望の直流の出力電圧に変換する昇降圧コンバータ用の制御回路に関する。   The present invention relates to a control circuit for a buck-boost converter that converts a DC input voltage into a desired DC output voltage.

入力直流電源から直流の入力電圧（以下、入力直流電圧という）を入力し、各種電子回路用に電源電圧となる直流の出力電圧（以下、出力直流電圧という）を出力する電源回路において、入力直流電圧が出力直流電圧に比べて大きい電圧から小さい電圧まで変動する場合、昇降圧コンバータが用いられる（例えば、特許文献１参照）。   In a power supply circuit that inputs a DC input voltage (hereinafter referred to as an input DC voltage) from an input DC power supply and outputs a DC output voltage (hereinafter referred to as an output DC voltage) that serves as a power supply voltage for various electronic circuits. When the voltage varies from a large voltage to a small voltage compared to the output DC voltage, a buck-boost converter is used (see, for example, Patent Document 1).

図４は、従来の昇降圧コンバータ用制御回路の回路構成を示す。制御回路１０は、昇降圧コンバータ１００の出力直流電圧Ｖｏに基づいて駆動信号ＤＲ１及びＤＲ２を生成し、昇降圧コンバータ１００を構成する降圧回路１０１及び昇圧回路１０２のそれぞれの動作を制御する。   FIG. 4 shows a circuit configuration of a conventional buck-boost converter control circuit. The control circuit 10 generates drive signals DR1 and DR2 based on the output DC voltage Vo of the step-up / down converter 100, and controls the operations of the step-down circuit 101 and the step-up circuit 102 that constitute the step-up / down converter 100.

具体的には、制御回路１０は、誤差増幅回路１１、反転増幅回路１２、発振器１３、比較器１４及び１５を備えている。誤差増幅回路１１は、電圧Ｖｏと目標値との誤差に基づいて誤差信号Ｖｅを生成する。誤差信号Ｖｅは、電圧Ｖｏが目標値よりも高いとき下降し、目標値よりも低いとき上昇する。反転増幅回路１２は、電位Ｅ１を軸として誤差信号Ｖｅを反転し、誤差信号Ｖｘを生成する。すなわち、誤差信号Ｖｘは、Ｖｘ＝２Ｅ１−Ｖｅで表される。発振器１３は、電位Ｅ１と電位Ｅ２（＜Ｅ１）との間を所定周期で増減する三角波状のランプ信号Ｖｔを生成する。比較器１４は、ランプ信号Ｖｔと誤差信号Ｖｅとを比較し、誤差信号Ｖｅの方が大きいときにＨレベルとなる駆動信号ＤＲ１を生成する。そして、比較器１５は、ランプ信号Ｖｔと誤差信号Ｖｘとを比較し、誤差信号Ｖｘの方が小さいときにＨレベルとなる駆動信号ＤＲ２を生成する。   Specifically, the control circuit 10 includes an error amplifier circuit 11, an inverting amplifier circuit 12, an oscillator 13, and comparators 14 and 15. The error amplifier circuit 11 generates an error signal Ve based on the error between the voltage Vo and the target value. The error signal Ve decreases when the voltage Vo is higher than the target value, and increases when the voltage Vo is lower than the target value. The inverting amplifier circuit 12 inverts the error signal Ve around the potential E1 to generate an error signal Vx. That is, the error signal Vx is represented by Vx = 2E1-Ve. The oscillator 13 generates a triangular wave ramp signal Vt that increases and decreases between the potential E1 and the potential E2 (<E1) at a predetermined cycle. The comparator 14 compares the ramp signal Vt and the error signal Ve, and generates the drive signal DR1 that becomes H level when the error signal Ve is larger. Then, the comparator 15 compares the ramp signal Vt with the error signal Vx, and generates a drive signal DR2 that becomes H level when the error signal Vx is smaller.

図５は、制御回路１０の動作波形図である。図５の左半部では、誤差信号Ｖｅは電位Ｅ１よりも低く、ランプ信号Ｖｔと交差しているが、誤差信号Ｖｘは電位Ｅ１よりも高く、ランプ信号Ｖｔと交差していない。したがって、駆動信号ＤＲ１はパルス状となって出力され、駆動信号ＤＲ２は一定レベル（この場合、Ｌレベル）のままである。このとき、昇降圧コンバータ１００は降圧コンバータとして動作する。   FIG. 5 is an operation waveform diagram of the control circuit 10. In the left half of FIG. 5, the error signal Ve is lower than the potential E1 and crosses the ramp signal Vt, but the error signal Vx is higher than the potential E1 and does not cross the ramp signal Vt. Therefore, the drive signal DR1 is output in the form of a pulse, and the drive signal DR2 remains at a constant level (in this case, L level). At this time, the buck-boost converter 100 operates as a step-down converter.

入力直流電圧Ｖｉの低下等によって出力直流電圧Ｖｏが目標値を下回ると、誤差信号Ｖｅは上昇し、誤差信号Ｖｘは下降する。やがて、誤差信号Ｖｅ及びＶｘは電位Ｅ１に達する。これ以降（図５の右半部）、誤差信号Ｖｅは電位Ｅ１よりも高くなりランプ信号Ｖｔと交差しないが、誤差信号Ｖｘは電位Ｅ１よりも低くなりランプ信号Ｖｔと交差するようになる。したがって、駆動信号ＤＲ１は一定レベル（この場合、Ｈレベル）のままとなり、駆動信号ＤＲ２はパルス状となって出力される。このとき、昇降圧コンバータ１００は昇圧コンバータとして動作する。
特許第３４４０３１４号公報 When the output DC voltage Vo falls below the target value due to a decrease in the input DC voltage Vi or the like, the error signal Ve rises and the error signal Vx falls. Eventually, the error signals Ve and Vx reach the potential E1. Thereafter (the right half of FIG. 5), the error signal Ve becomes higher than the potential E1 and does not cross the ramp signal Vt, but the error signal Vx becomes lower than the potential E1 and crosses the ramp signal Vt. Accordingly, the drive signal DR1 remains at a constant level (in this case, H level), and the drive signal DR2 is output in a pulse form. At this time, the buck-boost converter 100 operates as a boost converter.
Japanese Patent No. 3340314

従来の昇降圧コンバータ用制御回路では、ランプ信号Ｖｔが電位Ｅ１と電位Ｅ２との間を増減するのに対し、誤差信号Ｖｅ及びＶｘは２Ｅ１−Ｅ２以上になることがある。一方、昇降圧コンバータ用制御回路の電源電圧となる入力直流電圧Ｖｉは誤差信号Ｖｅ及びＶｘの最大値よりも大きくなければならないため（Ｖｉ＞２Ｅ１−Ｅ２）、電位Ｅ１は（Ｖｉ＋Ｅ２）／２よりも小さく設定しなければならない（Ｅ１＜（Ｖｉ＋Ｅ２）／２）。このため、ランプ信号Ｖｔの振幅を十分に大きく取ることができずに降圧回路１０１及び昇圧回路１０２におけるスイッチング周期のバラツキが大きくなり、昇降圧コンバータの動作が不安定になってしまう。   In the conventional buck-boost converter control circuit, the ramp signal Vt increases or decreases between the potential E1 and the potential E2, whereas the error signals Ve and Vx may be 2E1-E2 or more. On the other hand, the input DC voltage Vi serving as the power supply voltage for the buck-boost converter control circuit must be larger than the maximum values of the error signals Ve and Vx (Vi> 2E1-E2), so the potential E1 is from (Vi + E2) / 2. Must also be set smaller (E1 <(Vi + E2) / 2). For this reason, the amplitude of the ramp signal Vt cannot be made sufficiently large, and the variation of the switching cycle in the step-down circuit 101 and the step-up circuit 102 becomes large, and the operation of the step-up / down converter becomes unstable.

また、誤差信号Ｖｅ又は誤差信号Ｖｘがランプ信号Ｖｔの波形先端部分と交わる部分、すなわち、昇圧動作及びと降圧動作の遷移領域では、ランプ信号Ｖｔの波形先端部分の歪みによって、駆動信号ＤＲ１及びＤＲ２のデューティ比が急激に１００％又は０％になってしまうおそれがある。この結果、昇圧動作から降圧動作への遷移及びその逆の遷移がスムーズに行われずに昇降圧コンバータの動作が不安定になるといった問題がある。   Further, in the portion where the error signal Ve or the error signal Vx intersects the waveform tip portion of the ramp signal Vt, that is, in the transition region between the step-up operation and the step-down operation, the drive signals DR1 and DR2 are caused by distortion of the waveform tip portion of the ramp signal Vt. The duty ratio may suddenly become 100% or 0%. As a result, there is a problem in that the transition from the step-up operation to the step-down operation and vice versa is not performed smoothly, and the operation of the buck-boost converter becomes unstable.

上記問題に鑑み、本発明は、昇降圧コンバータを安定的に動作させる制御回路を実現することを課題とする。   In view of the above problems, an object of the present invention is to realize a control circuit that stably operates a buck-boost converter.

上記課題を解決するために本発明が講じた手段は、昇圧回路と降圧回路とを備えた昇降圧コンバータ用の制御回路として、昇降圧コンバータの出力電圧と目標値との誤差に基づいて、第１の誤差信号と、基準電位を軸として前記第１の誤差信号を反転した第２の誤差信号とを生成する出力検出回路と、基準電位を軸とするランプ信号を生成する発振器と、第１の誤差信号とランプ信号とを比較する第１の比較器と、第２の誤差信号とランプ信号とを比較する第２の比較器と、第１の比較器の出力と第２の比較器の出力との論理積に基づいて昇圧回路の動作を制御する昇圧制御回路と、第１の比較器の出力と第２の比較器の出力との論理和に基づいて降圧回路の動作を制御する降圧制御回路とを備えたものとする。   The means taken by the present invention to solve the above problems is a control circuit for a buck-boost converter including a booster circuit and a buck circuit, based on an error between the output voltage of the buck-boost converter and a target value. An output detection circuit that generates a first error signal, a second error signal obtained by inverting the first error signal with a reference potential as an axis, an oscillator that generates a ramp signal with the reference potential as an axis, A first comparator for comparing the error signal and the ramp signal, a second comparator for comparing the second error signal and the ramp signal, an output of the first comparator, and a second comparator A step-up control circuit that controls the operation of the step-up circuit based on the logical product with the output, and a step-down circuit that controls the operation of the step-down circuit based on the logical sum of the output of the first comparator and the output of the second comparator And a control circuit.

これによると、ランプ信号の振幅を比較的大きく取ることができ、また、ランプ信号の波形先端部分からずれて昇降圧コンバータの昇圧動作から降圧動作への遷移及びその逆の遷移が行われるため、昇降圧コンバータの動作が安定する。   According to this, the amplitude of the ramp signal can be relatively large, and the transition from the step-up / step-down operation of the buck-boost converter to the step-down operation and vice versa is performed by deviating from the waveform signal tip portion of the ramp signal. The operation of the buck-boost converter is stabilized.

具体的には、出力検出回路は、昇降圧コンバータの出力電圧と目標値との誤差に基づいて第１の誤差信号を生成する誤差増幅回路と、第１の誤差信号を受け、第２の誤差信号を生成する反転増幅回路とを有するものとする。   Specifically, the output detection circuit receives the first error signal and the error amplifier circuit that generates the first error signal based on the error between the output voltage of the buck-boost converter and the target value. And an inverting amplifier circuit for generating a signal.

なお、ランプ信号の変化の幅は、第１及び第２の誤差信号の変化の幅と同程度であることが好ましい。   Note that it is preferable that the change width of the ramp signal is approximately the same as the change width of the first and second error signals.

本発明によると、昇降圧コンバータの昇圧動作と降圧動作との切り替えがスムーズに行われ、昇降圧コンバータを安定的に動作させることができる。   According to the present invention, the step-up / step-down converter can be switched smoothly between the step-up operation and the step-down operation, and the step-up / step-down converter can be operated stably.

以下、本発明を実施するための最良の形態について、図面を参照しながら説明する。   The best mode for carrying out the present invention will be described below with reference to the drawings.

図１は、本発明の一実施形態に係る昇降圧コンバータ用制御回路の回路構成を示す。制御回路１０Ａは、昇降圧コンバータ１００の出力直流電圧Ｖｏに基づいて駆動信号ＤＲ１及びＤＲ２を生成し、昇降圧コンバータ１００を構成する降圧回路１０１及び昇圧回路１０２のそれぞれの動作を制御する。   FIG. 1 shows a circuit configuration of a buck-boost converter control circuit according to an embodiment of the present invention. The control circuit 10 </ b> A generates drive signals DR <b> 1 and DR <b> 2 based on the output DC voltage Vo of the step-up / down converter 100 and controls the operations of the step-down circuit 101 and the step-up circuit 102 that constitute the step-up / down converter 100.

具体的には、制御回路１０Ａは、誤差増幅回路１１、反転増幅回路１２、発振器１３、比較器１４及び１５、降圧制御回路１６、及び昇圧制御回路１７を備えている。また、誤差増幅回路１１及び反転増幅回路１２は出力検出回路１８を構成している。誤差増幅回路１１は、昇降圧コンバータ１００の出力直流電圧Ｖｏと目標値との誤差に基づいて誤差信号Ｖｅを生成する。誤差信号Ｖｅは、電圧Ｖｏが目標値よりも高いとき下降し、目標値よりも低いとき上昇する。反転増幅回路１２は、基準電位Ｅｔを軸として誤差信号Ｖｅを反転し、誤差信号Ｖｘを生成する。すなわち、誤差信号Ｖｘは、Ｖｘ＝２Ｅｔ−Ｖｅで表される。発振器１３は、基準電位Ｅｔを軸として振幅ΔＥの三角波状のランプ信号Ｖｔを生成する。比較器１４は、ランプ信号Ｖｔと誤差信号Ｖｅとを比較し、誤差信号Ｖｅの方が大きいときにＨレベルとなる信号Ｖ１を生成する。比較器１５は、ランプ信号Ｖｔと誤差信号Ｖｘとを比較し、誤差信号Ｖｘの方が小さいときにＨレベルとなる信号Ｖ２を生成する。降圧制御回路１６は、ＯＲゲートで構成されており、信号Ｖ１と信号Ｖ２との論理和である駆動信号ＤＲ１を出力する。そして、昇圧制御回路１７は、ＡＮＤゲートで構成されており、信号Ｖ１と信号Ｖ２との論理積である駆動信号ＤＲ２を出力する。   Specifically, the control circuit 10A includes an error amplifier circuit 11, an inverting amplifier circuit 12, an oscillator 13, comparators 14 and 15, a step-down control circuit 16, and a step-up control circuit 17. The error amplifier circuit 11 and the inverting amplifier circuit 12 constitute an output detection circuit 18. The error amplifier circuit 11 generates an error signal Ve based on the error between the output DC voltage Vo of the step-up / down converter 100 and the target value. The error signal Ve decreases when the voltage Vo is higher than the target value, and increases when the voltage Vo is lower than the target value. The inverting amplifier circuit 12 inverts the error signal Ve around the reference potential Et to generate an error signal Vx. That is, the error signal Vx is represented by Vx = 2 Et−Ve. The oscillator 13 generates a triangular wave ramp signal Vt having an amplitude ΔE around the reference potential Et. The comparator 14 compares the ramp signal Vt and the error signal Ve, and generates a signal V1 that becomes H level when the error signal Ve is larger. The comparator 15 compares the ramp signal Vt and the error signal Vx, and generates a signal V2 that becomes H level when the error signal Vx is smaller. The step-down control circuit 16 is composed of an OR gate, and outputs a drive signal DR1 that is a logical sum of the signal V1 and the signal V2. The boost control circuit 17 is composed of an AND gate, and outputs a drive signal DR2 that is a logical product of the signal V1 and the signal V2.

図２は、本実施形態に係る制御回路１０Ａの動作波形図である。図２の左半部では、誤差信号Ｖｅは基準電位Ｅｔよりも低いところでランプ信号Ｖｔと交差しており、誤差信号Ｖｘは基準電位Ｅｔよりも高いところでランプ信号Ｖｔと交差している。したがって、信号Ｖ１及びＶ２は相補的にＨレベルとなり、その論理和である駆動信号ＤＲ１はパルス状となって出力される一方、その論理積である駆動信号ＤＲ２はＬレベルのままとなる。このとき、昇降圧コンバータ１００は降圧コンバータとして動作する。   FIG. 2 is an operation waveform diagram of the control circuit 10A according to the present embodiment. In the left half of FIG. 2, the error signal Ve intersects with the ramp signal Vt when it is lower than the reference potential Et, and the error signal Vx intersects with the ramp signal Vt when it is higher than the reference potential Et. Therefore, the signals V1 and V2 complementarily become H level, and the drive signal DR1 which is the logical sum thereof is output in a pulse form, while the drive signal DR2 which is the logical product remains at the L level. At this time, the buck-boost converter 100 operates as a step-down converter.

入力直流電圧Ｖｉの低下等によって出力直流電圧Ｖｏが目標値を下回ると、誤差信号Ｖｅは上昇し、誤差信号Ｖｘは下降する。やがて、誤差信号Ｖｅ及びＶｘは基準電位Ｅｔに達する。これ以降（図２の右半部）、誤差信号Ｖｅは基準電位Ｅｔよりも高いところでランプ信号Ｖｔと交差し、誤差信号Ｖｘは基準電位Ｅｔよりも低いところでランプ信号Ｖｔと交差するようになる。したがって、信号Ｖ１及びＶ２は相補的にＬレベルとなり、その論理和である駆動信号ＤＲ１はＨレベルのままとなる一方、その論理積である駆動信号ＤＲ２はパルス状となって出力される。このとき、昇降圧コンバータ１００は昇圧コンバータとして動作する。   When the output DC voltage Vo falls below the target value due to a decrease in the input DC voltage Vi or the like, the error signal Ve rises and the error signal Vx falls. Eventually, the error signals Ve and Vx reach the reference potential Et. Thereafter (the right half of FIG. 2), the error signal Ve crosses the ramp signal Vt when it is higher than the reference potential Et, and the error signal Vx crosses the ramp signal Vt when it is lower than the reference potential Et. Therefore, the signals V1 and V2 are complementarily at the L level, and the drive signal DR1 that is the logical sum remains at the H level, while the drive signal DR2 that is the logical product is output in a pulse form. At this time, the buck-boost converter 100 operates as a boost converter.

以上、本実施形態に係る制御回路１０Ａによると、昇降圧コンバータ１００の昇圧動作から降圧動作への遷移及びその逆の遷移は、誤差信号Ｖｅ又は誤差信号Ｖｘがランプ信号Ｖｔの振幅中心付近の基準電位Ｅ１と交わる部分で起きる。したがって、ランプ信号Ｖｔの波形先端部分の歪みにかかわらず、昇降圧コンバータ１００はスムーズに昇圧動作から降圧動作への遷移及びその逆の遷移をすることができる。   As described above, according to the control circuit 10A according to the present embodiment, the transition from the step-up operation to the step-down operation of the step-up / step-down converter 100 and vice versa are the reference where the error signal Ve or the error signal Vx is near the amplitude center of the ramp signal Vt. Occurs at a portion where the potential E1 intersects. Therefore, the buck-boost converter 100 can smoothly make a transition from the step-up operation to the step-down operation and vice versa regardless of the distortion at the front end of the waveform of the ramp signal Vt.

なお、誤差信号Ｖｅ及びＶｘは、ランプ信号Ｖｔの最大値であるＥｔ＋ΔＥ以上であればよい。好ましくは、ランプ信号Ｖｔの変化の幅と誤差信号Ｖｅ及びＶｘの変化の幅とを同程度にする。これにより、ランプ信号Ｖｔの振幅を十分に大きく取ることができ、昇降圧コンバータ１００の動作の安定化を図ることができる。   The error signals Ve and Vx may be equal to or greater than Et + ΔE, which is the maximum value of the ramp signal Vt. Preferably, the change width of the ramp signal Vt and the change widths of the error signals Ve and Vx are approximately the same. Thereby, the amplitude of ramp signal Vt can be made sufficiently large, and the operation of buck-boost converter 100 can be stabilized.

また、必ずしもランプ信号Ｖｔの中心である基準電位Ｅｔを軸として誤差信号Ｖｅを反転して誤差信号Ｖｘを生成しなくてもよい。すなわち、多少の誤差は許容される。図３は、ランプ信号Ｖｔの中心が基準電位Ｅｔよりもわずかに高い場合の動作波形を示す。この場合、誤差信号Ｖｅ及びＶｘが高くずれるため、信号Ｖ１のパルス幅は大きく、信号Ｖ２のパルス幅は小さくなる。このため、スイッチング２周期ごとに駆動信号ＤＲ１及びＤＲ２のパルス幅が揃う親子発振と呼ばれる現象が生じる。しかし、この現象は帰還系の異常発振動作とは異なるうえ、その度合いも小さいため、昇降圧コンバータ１００の制御に関して問題となることはほとんどない。   Further, the error signal Vx may not be generated by inverting the error signal Ve around the reference potential Et that is the center of the ramp signal Vt. That is, some errors are allowed. FIG. 3 shows an operation waveform when the center of the ramp signal Vt is slightly higher than the reference potential Et. In this case, since the error signals Ve and Vx are highly shifted, the pulse width of the signal V1 is large and the pulse width of the signal V2 is small. For this reason, a phenomenon called parent-child oscillation occurs in which the pulse widths of the drive signals DR1 and DR2 are aligned every two switching cycles. However, since this phenomenon is different from the abnormal oscillation operation of the feedback system and its degree is small, there is almost no problem with the control of the buck-boost converter 100.

また、図１では、発振器１３は３つの電位Ｅｔ＋ΔＥ、Ｅｔ及びＥｔ−ΔＥを受けているが、本発明はこの構成に限定されるものではない。例えば、発振器１３は、基準電位Ｅｔと振幅に相当する電圧ΔＥの二つを受けてランプ信号Ｖｔを生成するようにしてもよいし、また、ランプ信号Ｖｔの上限及び下限の電位Ｅｔ＋ΔＥ及びＥｔ−ΔＥを受けてランプ信号Ｖｔ及び基準電位Ｅｔを生成するようにしてもよい。また、反転増幅回路１２は１個のオペアンプと２個の抵抗から構成される一般的な構成としているが、これ以外の構成であってもよい。また、降圧制御回路１６は、ＯＲゲート以外にも、信号Ｖ１と信号Ｖ２との論理和に基づいて駆動信号ＤＲ１を生成するものであればよい。同様に、昇圧制御回路１７は、ＡＮＤゲート以外にも、信号Ｖ１と信号Ｖ２との論理積に基づいて駆動信号ＤＲ２を生成するものであればよい。   In FIG. 1, the oscillator 13 receives three potentials Et + ΔE, Et, and Et−ΔE, but the present invention is not limited to this configuration. For example, the oscillator 13 may generate the ramp signal Vt by receiving two of the reference potential Et and the voltage ΔE corresponding to the amplitude, or the upper and lower potentials Et + ΔE and Et− of the ramp signal Vt. The ramp signal Vt and the reference potential Et may be generated in response to ΔE. The inverting amplifier circuit 12 has a general configuration including one operational amplifier and two resistors, but may have a configuration other than this. In addition to the OR gate, the step-down control circuit 16 only needs to generate the drive signal DR1 based on the logical sum of the signal V1 and the signal V2. Similarly, the boost control circuit 17 may be any circuit that generates the drive signal DR2 based on the logical product of the signal V1 and the signal V2 other than the AND gate.

また、図１では、出力検出回路１８は誤差増幅回路１１及び反転増幅回路１２から構成されているが、本発明はこの構成に限定されるものではない。例えば、誤差増幅回路１１を差動増幅回路として構成する場合には、誤差増幅回路１１によって誤差信号Ｖｅ及びＶｘを生成することができる。すなわち、出力検出回路１８は誤差増幅回路１１のみで構成されることとなる。この場合、誤差増幅回路１１に与えられる電源電圧をＥｂとすると、基準電圧ＥｔはＥｔ＝Ｅｂ／２を満たすように設定すればよい。   In FIG. 1, the output detection circuit 18 includes the error amplifier circuit 11 and the inverting amplifier circuit 12, but the present invention is not limited to this configuration. For example, when the error amplifier circuit 11 is configured as a differential amplifier circuit, the error signals Ve and Vx can be generated by the error amplifier circuit 11. That is, the output detection circuit 18 is configured only by the error amplification circuit 11. In this case, if the power supply voltage supplied to the error amplifier circuit 11 is Eb, the reference voltage Et may be set so as to satisfy Et = Eb / 2.

また、本発明に係る制御回路の制御対象となる昇降圧コンバータは図１に示したものに限られない。本発明に係る制御回路は、およそ昇圧回路と降圧回路とを備えた昇降圧コンバータ一般に適合する。   Further, the buck-boost converter to be controlled by the control circuit according to the present invention is not limited to that shown in FIG. The control circuit according to the present invention is generally compatible with a step-up / down converter generally including a step-up circuit and a step-down circuit.

本発明に係る制御回路は、昇降圧コンバータの動作を安定化させるため、安定的な電源供給が要求される装置の電源回路に有用である。   The control circuit according to the present invention is useful for a power supply circuit of a device that requires a stable power supply in order to stabilize the operation of the buck-boost converter.

本発明の一実施形態に係る昇降圧コンバータ用制御回路の回路構成図である。It is a circuit block diagram of the control circuit for buck-boost converters concerning one Embodiment of this invention. 図１に示した制御回路の動作波形図である。FIG. 2 is an operation waveform diagram of the control circuit shown in FIG. 1. 誤差信号の反転軸がずれた場合の図１に示した制御回路の動作波形図である。FIG. 2 is an operation waveform diagram of the control circuit shown in FIG. 1 when an inversion axis of an error signal is shifted. 従来の昇降圧コンバータ用制御回路の回路構成図である。It is a circuit block diagram of the conventional control circuit for buck-boost converters. 図４に示した制御回路の動作波形図である。FIG. 5 is an operation waveform diagram of the control circuit shown in FIG. 4.

符号の説明Explanation of symbols

１０Ａ 制御回路
１１ 誤差増幅回路
１２ 反転増幅回路
１３ 発振器
１４ 比較器（第１の比較器）
１５ 比較器（第２の比較器）
１６ 昇圧制御回路
１７ 降圧制御回路
１８ 出力検出回路 10A Control circuit 11 Error amplifier circuit 12 Inverting amplifier circuit 13 Oscillator 14 Comparator (first comparator)
15 comparator (second comparator)
16 step-up control circuit 17 step-down control circuit 18 output detection circuit

Claims (3)

昇圧回路と降圧回路とを備えた昇降圧コンバータ用の制御回路であって、
前記昇降圧コンバータの出力電圧と目標値との誤差に基づいて、第１の誤差信号と、基準電位を軸として前記第１の誤差信号を反転した第２の誤差信号とを生成する出力検出回路と、
前記基準電位を軸とするランプ信号を生成する発振器と、
前記第１の誤差信号と前記ランプ信号とを比較する第１の比較器と、
前記第２の誤差信号と前記ランプ信号とを比較する第２の比較器と、
前記第１の比較器の出力と前記第２の比較器の出力との論理積に基づいて前記昇圧回路の動作を制御する昇圧制御回路と、
前記第１の比較器の出力と前記第２の比較器の出力との論理和に基づいて前記降圧回路の動作を制御する降圧制御回路とを備えた
ことを特徴とする制御回路。 A control circuit for a buck-boost converter having a booster circuit and a step-down circuit,
An output detection circuit that generates a first error signal and a second error signal obtained by inverting the first error signal with a reference potential as an axis based on an error between the output voltage of the buck-boost converter and a target value When,
An oscillator that generates a ramp signal around the reference potential;
A first comparator for comparing the first error signal and the ramp signal;
A second comparator for comparing the second error signal and the ramp signal;
A step-up control circuit that controls the operation of the step-up circuit based on the logical product of the output of the first comparator and the output of the second comparator;
A control circuit comprising: a step-down control circuit that controls an operation of the step-down circuit based on a logical sum of an output of the first comparator and an output of the second comparator. 請求項１に記載の制御回路において、
前記出力検出回路は、
前記昇降圧コンバータの出力電圧と前記目標値との誤差に基づいて前記第１の誤差信号を生成する誤差増幅回路と、
前記第１の誤差信号を受け、前記第２の誤差信号を生成する反転増幅回路とを有する
ことを特徴とする制御回路。 The control circuit according to claim 1,
The output detection circuit includes:
An error amplification circuit that generates the first error signal based on an error between the output voltage of the step-up / down converter and the target value;
A control circuit comprising: an inverting amplifier circuit that receives the first error signal and generates the second error signal. 請求項１に記載の制御回路において、
前記ランプ信号の変化の幅は、前記第１及び第２の誤差信号の変化の幅と同程度である
ことを特徴とする制御回路。 The control circuit according to claim 1,
The width of change of the ramp signal is approximately the same as the width of change of the first and second error signals.
JP2005287449A 2005-09-30 2005-09-30 Control circuit for step-up/down converter Pending JP2007104741A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011229214A (en) * 2010-04-15 2011-11-10 Fujitsu Semiconductor Ltd Control circuit and method for controlling switching power supply
CN114301285A (en) * 2021-12-28 2022-04-08 上海晶丰明源半导体股份有限公司 Controller, switching converter and control method for switching converter

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002186249A (en) * 2000-12-14 2002-06-28 Fuji Electric Co Ltd Step up/step down dc-dc converter
JP2003088109A (en) * 2001-09-13 2003-03-20 Denso Corp Switching power supply and navigation device
JP2004147436A (en) * 2002-10-24 2004-05-20 Sanken Electric Co Ltd Dc-dc converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002186249A (en) * 2000-12-14 2002-06-28 Fuji Electric Co Ltd Step up/step down dc-dc converter
JP2003088109A (en) * 2001-09-13 2003-03-20 Denso Corp Switching power supply and navigation device
JP2004147436A (en) * 2002-10-24 2004-05-20 Sanken Electric Co Ltd Dc-dc converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011229214A (en) * 2010-04-15 2011-11-10 Fujitsu Semiconductor Ltd Control circuit and method for controlling switching power supply
CN114301285A (en) * 2021-12-28 2022-04-08 上海晶丰明源半导体股份有限公司 Controller, switching converter and control method for switching converter
CN114301285B (en) * 2021-12-28 2023-12-26 上海晶丰明源半导体股份有限公司 Controller, switching converter and control method for switching converter

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