JP2005524970A - トレンチ型パワーmosゲートデバイス - Google Patents
トレンチ型パワーmosゲートデバイス Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 108091006146 Channels Proteins 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 9
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
Description
・トレンチ内の厚くしている底部酸化膜;
・単純化している電流流路;
・末端領域にソースが存在しないこと;
・(重要なコンタクト整合の問題、及びメタルのステップカバレージの問題をなくするため)シリコンの中へコンタクトをエッチングしないこと;
・トレンチ内のポリシリコンゲートの頂部を覆う堆積された酸化膜
を用いた構造を提供する。
図3は、図1及び図2のデバイスの1つの改良例を示した図で、ゲートポリシリコン上にシリサイドを有する図1の横断面図である。導電性ポリシリコン充填物17,18は、ゲート端子への有効横方向ゲート抵抗を低下させる金属シリサイド(silicide)層40,41によりそれぞれ被覆される。さらに、それぞれトレンチ13,14の底部45,46においてゲート酸化膜15,16を厚くしている。その上さらに、図3において、より厚いハードマスク(hardmask)を使用し、かつ導電性ポリシリコン充填物17,18の中心における凹所をハードマスク下方に到達させない。また、図3において、デバイスのQgを決定するソース/ゲートの重複は、拡散によってのみ形成される。最後に、ゲート酸化膜15,16は、ポリシリコンエッチングプラズマから、またソース埋め込みプラズマから遮蔽されている。
ステップ2;次に、N−ドリフト領域11の頂部中にP形チャネル埋め込み部を形成する。
ステップ3;次に、P型チャネル埋め込み部の頂部に、厚さ約3500Åまで窒化膜を付着させる。
ステップ5;次に、チャネルのドライブ(drive)、P埋め込みのドライブを約1100℃で約30分間実施して、P型チャネル領域12を形成する。
ステップ6;次に、フィールド酸化ステップを実施して、厚さ約5000Åまで酸化膜を形成する。
ステップ8;次に、犠牲(sacrificial)酸化膜(450Å)及びエッチングを実施する。
ステップ9;次に、パッド酸化膜240Åを成長させ、続いて,トレンチ壁上に、また壁の間のメサ(mesa)表面頂部上に、ゲート窒化膜を付着させる。
ステップ11;次に、酸化膜45をトレンチ底部に2000Åまで成長させる。
ステップ12;次に、湿式窒化膜エッチングにより、垂直トレンチ壁の窒化膜を除去する。
ステップ14;次に、ウエハ上及びトレンチの中へ、厚さ5000Åまでポリシリコンを堆積させる。
ステップ15;次に、POCl堆積を行い、かつドライブを実施してポリシリコン物質17,18を導電性とする。
ステップ17;次に、ポリ酸化膜(polyoxide)を約450Åまで形成する。
ステップ18;次に、窒化膜上の酸化膜のエッチングを実施し、窒化膜を約1000Åだけ横に後退させて、ソース埋め込みのために、トレンチ間のメサのコーナを空にする。
ステップ20;その後、かつ本発明の重要な特徴に従って、厚さ約4000Åまで低密度TEOS堆積を実施して、図4及び図5における酸化膜プラグ20を形成する。酸化膜プラグは成長させないで、堆積させ、デバイスの信頼性向上をもたらす点が注目に値する。
ステップ24;次に、標準的な仕上げステップを使用し、それに続いてN+ウエハ10の底部にバックメタル(back metal)(図示されない)を形成する。
Claims (7)
- N−ドリフト領域及び該N−ドリフト領域の頂部に設けられたP型チャネルを有するシリコンダイと、
該シリコンダイの頂部内側に向けて設けられ、かつ前記シリコンダイを通って前記N−ドリフト領域内まで直角に延在し、壁上にゲート誘電体を有し、かつ導電性ポリシリコン充填物で前記シリコンダイの頂部の表面下方の高さまで充填された間隔を有する複数のトレンチと、
前記導電性ポリシリコン充填物の各々の頂部に設けられ、かつ少なくとも前記頂部まで前記トレンチを充填している酸化膜プラグと、
前記トレンチの壁の頂部内側に設けられ、かつ前記トレンチの頂部に短い横延長部を有し、所定の深さで前記導電性ポリシリコン充填物の頂部下方に広がり、互いに間隔を有するN+ソース拡散部と、
前記シリコンダイの頂部を覆うとともに、前記N+ソース領域の頂部表面に接触し、かつ該N+ソース領域間の前記Pチャネル領域に接触しているソース電極と
を備えたことを特徴とするトレンチ型パワーMOSゲートデバイス。 - 前記シリコンダイの前記頂部表面と、前記酸化物プラグの頂部表面とは、実質的に共通の平面内にあることを特徴とする請求項1に記載のトレンチ型パワーMOSゲートデバイス。
- 前記酸化物プラグは、堆積された酸化膜であることを特徴とする請求項1または2に記載のトレンチ型パワーMOSゲートデバイス。
- 前記ゲート誘電体は、成長している酸化膜であることを特徴とする請求項1又は2に記載のトレンチ型パワーMOSゲートデバイス。
- 前記トレンチの各々の底部は、前記ゲート誘電体の厚さよりも大きな厚さを有する酸化膜で裏張りされていることを特徴とする請求項1乃至4のいずれかに記載のトレンチ型パワーMOSゲートデバイス。
- 活性領域を取り囲むトレンチ末端部を備え、該トレンチ末端部はフィールド酸化膜層で被覆され、該フィールド酸化膜は導電性ポリシリコンで覆われ、該導電性ポリシリコンは堆積された酸化膜により覆われていることを特徴とする請求項1乃至5のいずれかに記載のトレンチ型パワーMOSゲートデバイス。
- シリコン基板中に垂直なトレンチを有し、該垂直なトレンチは、垂直な壁上にゲート酸化膜を有し、かつ導電性ポリシリコンを前記シリコン基板の頂部下方の高さまで充填し、前記導電性ポリシリコンの頂部から前記シリコン基板の頂部までの開口部には、堆積された酸化膜を充填していることを特徴とするトレンチ型パワーMOSゲートデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31751601P | 2001-09-05 | 2001-09-05 | |
US10/234,303 US7045859B2 (en) | 2001-09-05 | 2002-08-30 | Trench fet with self aligned source and contact |
PCT/US2002/028067 WO2003021639A2 (en) | 2001-09-05 | 2002-09-03 | Trench fet with self aligned source and contact |
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JP2005524970A true JP2005524970A (ja) | 2005-08-18 |
JP4005019B2 JP4005019B2 (ja) | 2007-11-07 |
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US (3) | US7045859B2 (ja) |
JP (1) | JP4005019B2 (ja) |
KR (1) | KR100589252B1 (ja) |
CN (1) | CN100365826C (ja) |
AU (1) | AU2002326812A1 (ja) |
DE (1) | DE10297177B4 (ja) |
TW (1) | TW561517B (ja) |
WO (1) | WO2003021639A2 (ja) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006060184A (ja) * | 2004-07-23 | 2006-03-02 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
JP2008270811A (ja) * | 2007-04-19 | 2008-11-06 | Vishay-Siliconix | トレンチ金属酸化物半導体 |
JP2009260271A (ja) * | 2008-03-28 | 2009-11-05 | Toshiba Corp | 半導体装置及びdc−dcコンバータ |
JP2010534921A (ja) * | 2007-04-03 | 2010-11-11 | ビシャイ‐シリコニックス | 自己整合トレンチmosfet及びその製造方法 |
US9431530B2 (en) | 2009-10-20 | 2016-08-30 | Vishay-Siliconix | Super-high density trench MOSFET |
US9437729B2 (en) | 2007-01-08 | 2016-09-06 | Vishay-Siliconix | High-density power MOSFET with planarized metalization |
US9443974B2 (en) | 2009-08-27 | 2016-09-13 | Vishay-Siliconix | Super junction trench power MOSFET device fabrication |
WO2017149624A1 (ja) * | 2016-02-29 | 2017-09-08 | 新電元工業株式会社 | パワー半導体装置及びパワー半導体装置の製造方法 |
US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
JP2019024138A (ja) * | 2013-08-28 | 2019-02-14 | ローム株式会社 | 半導体装置 |
JP2019024133A (ja) * | 2012-08-21 | 2019-02-14 | ローム株式会社 | 半導体装置 |
US10234486B2 (en) | 2014-08-19 | 2019-03-19 | Vishay/Siliconix | Vertical sense devices in vertical trench MOSFET |
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- 2002-09-03 JP JP2003525887A patent/JP4005019B2/ja not_active Expired - Lifetime
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- 2002-09-04 TW TW091120210A patent/TW561517B/zh not_active IP Right Cessation
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US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
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WO2003021639A3 (en) | 2003-07-31 |
US7397083B2 (en) | 2008-07-08 |
WO2003021639A2 (en) | 2003-03-13 |
US20060157782A1 (en) | 2006-07-20 |
DE10297177T5 (de) | 2004-08-26 |
AU2002326812A1 (en) | 2003-03-18 |
TW561517B (en) | 2003-11-11 |
JP4005019B2 (ja) | 2007-11-07 |
US20080061365A1 (en) | 2008-03-13 |
US7045859B2 (en) | 2006-05-16 |
KR20040029158A (ko) | 2004-04-03 |
CN100365826C (zh) | 2008-01-30 |
CN1552102A (zh) | 2004-12-01 |
US7301200B2 (en) | 2007-11-27 |
KR100589252B1 (ko) | 2006-06-19 |
DE10297177B4 (de) | 2016-06-16 |
US20030085422A1 (en) | 2003-05-08 |
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