IN2012DN00196A - - Google Patents
Info
- Publication number
- IN2012DN00196A IN2012DN00196A IN196DEN2012A IN2012DN00196A IN 2012DN00196 A IN2012DN00196 A IN 2012DN00196A IN 196DEN2012 A IN196DEN2012 A IN 196DEN2012A IN 2012DN00196 A IN2012DN00196 A IN 2012DN00196A
- Authority
- IN
- India
- Prior art keywords
- size
- superpage
- pages
- operating system
- entry
- Prior art date
Links
- 230000004044 response Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/652—Page size control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/496,335 US8195917B2 (en) | 2009-07-01 | 2009-07-01 | Extended page size using aggregated small pages |
PCT/US2010/040625 WO2011002900A1 (en) | 2009-07-01 | 2010-06-30 | Extended page size using aggregated small pages |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2012DN00196A true IN2012DN00196A (ko) | 2015-04-24 |
Family
ID=43411433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN196DEN2012 IN2012DN00196A (ko) | 2009-07-01 | 2010-06-30 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8195917B2 (ko) |
JP (1) | JP2012532381A (ko) |
KR (1) | KR101563659B1 (ko) |
CN (1) | CN102473091B (ko) |
GB (1) | GB2485082B (ko) |
IN (1) | IN2012DN00196A (ko) |
WO (1) | WO2011002900A1 (ko) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8527736B1 (en) * | 2010-09-07 | 2013-09-03 | Adtran, Inc. | Systems and methods for improving address translation speed |
US8943296B2 (en) | 2011-04-28 | 2015-01-27 | Vmware, Inc. | Virtual address mapping using rule based aliasing to achieve fine grained page translation |
US9767039B2 (en) * | 2011-07-18 | 2017-09-19 | Vmware, Inc. | Increasing granularity of dirty bit information in hardware assisted memory management systems |
US9753860B2 (en) | 2012-06-14 | 2017-09-05 | International Business Machines Corporation | Page table entry consolidation |
US9092359B2 (en) * | 2012-06-14 | 2015-07-28 | International Business Machines Corporation | Identification and consolidation of page table entries |
US9811472B2 (en) | 2012-06-14 | 2017-11-07 | International Business Machines Corporation | Radix table translation of memory |
US8954707B2 (en) * | 2012-08-03 | 2015-02-10 | International Business Machines Corporation | Automatic use of large pages |
JP5958195B2 (ja) * | 2012-08-31 | 2016-07-27 | 日本電気株式会社 | 仮想記憶管理システム、仮想記憶管理装置、仮想記憶初期化方法および仮想記憶初期化プログラム |
US9058268B1 (en) | 2012-09-20 | 2015-06-16 | Matrox Graphics Inc. | Apparatus, system and method for memory management |
US9459877B2 (en) | 2012-12-21 | 2016-10-04 | Advanced Micro Devices, Inc. | Nested speculative regions for a synchronization facility |
US8966220B2 (en) | 2013-01-15 | 2015-02-24 | International Business Machines Corporation | Optimizing large page processing |
US9164915B2 (en) | 2013-01-15 | 2015-10-20 | International Business Machines Corporation | Reserving fixed page areas in real storage increments |
KR102069857B1 (ko) * | 2013-02-28 | 2020-01-23 | 삼성전자주식회사 | 자체-학습을 통해 원래 이미지를 회전하는 방법과 상기 방법을 수행할 수 있는 장치들 |
US9563571B2 (en) | 2014-04-25 | 2017-02-07 | Apple Inc. | Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management |
US9507726B2 (en) * | 2014-04-25 | 2016-11-29 | Apple Inc. | GPU shared virtual memory working set management |
WO2016175814A1 (en) | 2015-04-30 | 2016-11-03 | Hewlett Packard Enterprise Development Lp | Mapping apertures of different sizes |
US10310854B2 (en) | 2015-06-30 | 2019-06-04 | International Business Machines Corporation | Non-faulting compute instructions |
US10061539B2 (en) * | 2015-06-30 | 2018-08-28 | International Business Machines Corporation | Inaccessibility status indicator |
US10162525B2 (en) | 2015-09-11 | 2018-12-25 | Red Hat Israel, Ltd. | Translating access requests for a multi-level page data structure |
CN106940623B (zh) * | 2016-01-04 | 2020-06-09 | 群联电子股份有限公司 | 存储器管理方法、存储器控制电路单元及存储器储存装置 |
US10108550B2 (en) | 2016-09-22 | 2018-10-23 | Google Llc | Memory management supporting huge pages |
US10282296B2 (en) | 2016-12-12 | 2019-05-07 | Intel Corporation | Zeroing a cache line |
US10241925B2 (en) | 2017-02-15 | 2019-03-26 | Ati Technologies Ulc | Selecting a default page size in a variable page size TLB |
US10282309B2 (en) | 2017-02-24 | 2019-05-07 | Advanced Micro Devices, Inc. | Per-page control of physical address space distribution among memory modules |
US10339068B2 (en) | 2017-04-24 | 2019-07-02 | Advanced Micro Devices, Inc. | Fully virtualized TLBs |
US10228991B2 (en) | 2017-06-28 | 2019-03-12 | Qualcomm Incorporated | Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems |
KR101942663B1 (ko) * | 2017-09-28 | 2019-01-25 | 한국과학기술원 | 가상 메모리 주소 변환 효율화를 위한 연속성 활용 주소 변환 방법 및 시스템 |
CN108415782A (zh) * | 2018-02-23 | 2018-08-17 | 携程旅游网络技术(上海)有限公司 | 应用程序的控件通信方法、装置、电子设备、存储介质 |
US11204879B2 (en) * | 2019-06-06 | 2021-12-21 | Arm Limited | Memory management circuitry managing data transactions and address translations between an upstream device and a downstream device |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6112285A (en) * | 1997-09-23 | 2000-08-29 | Silicon Graphics, Inc. | Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support |
US6134602A (en) | 1997-09-24 | 2000-10-17 | Microsoft Corporation | Application programming interface enabling application programs to group code and data to control allocation of physical memory in a virtual memory system |
US20040117594A1 (en) * | 2002-12-13 | 2004-06-17 | Vanderspek Julius | Memory management method |
US8417913B2 (en) * | 2003-11-13 | 2013-04-09 | International Business Machines Corporation | Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages |
US7444493B2 (en) * | 2004-09-30 | 2008-10-28 | Intel Corporation | Address translation for input/output devices using hierarchical translation tables |
US8843727B2 (en) * | 2004-09-30 | 2014-09-23 | Intel Corporation | Performance enhancement of address translation using translation tables covering large address spaces |
US7395405B2 (en) * | 2005-01-28 | 2008-07-01 | Intel Corporation | Method and apparatus for supporting address translation in a virtual machine environment |
US7395406B2 (en) * | 2005-05-12 | 2008-07-01 | International Business Machines Corporation | System and method of large page handling in a virtual memory system |
US7437529B2 (en) * | 2005-06-16 | 2008-10-14 | International Business Machines Corporation | Method and mechanism for efficiently creating large virtual memory pages in a multiple page size environment |
US7376808B2 (en) * | 2006-01-31 | 2008-05-20 | International Business Machines Corporation | Method and system for predicting the performance benefits of mapping subsets of application data to multiple page sizes |
US7747838B2 (en) * | 2007-05-19 | 2010-06-29 | International Business Machines Corporation | Method and apparatus for dynamically adjusting page size in a virtual memory range |
US8078827B2 (en) * | 2007-07-05 | 2011-12-13 | International Business Machines Corporation | Method and apparatus for caching of page translations for virtual machines |
US7793070B2 (en) * | 2007-07-12 | 2010-09-07 | Qnx Software Systems Gmbh & Co. Kg | Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics |
US7783859B2 (en) * | 2007-07-12 | 2010-08-24 | Qnx Software Systems Gmbh & Co. Kg | Processing system implementing variable page size memory organization |
US9244855B2 (en) * | 2007-12-31 | 2016-01-26 | Intel Corporation | Method, system, and apparatus for page sizing extension |
US8688894B2 (en) * | 2009-09-03 | 2014-04-01 | Pioneer Chip Technology Ltd. | Page based management of flash storage |
-
2009
- 2009-07-01 US US12/496,335 patent/US8195917B2/en active Active
-
2010
- 2010-06-30 KR KR1020127000750A patent/KR101563659B1/ko active IP Right Grant
- 2010-06-30 JP JP2012518596A patent/JP2012532381A/ja active Pending
- 2010-06-30 CN CN201080030133.3A patent/CN102473091B/zh active Active
- 2010-06-30 IN IN196DEN2012 patent/IN2012DN00196A/en unknown
- 2010-06-30 GB GB1200020.4A patent/GB2485082B/en active Active
- 2010-06-30 WO PCT/US2010/040625 patent/WO2011002900A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US20110004739A1 (en) | 2011-01-06 |
WO2011002900A1 (en) | 2011-01-06 |
KR101563659B1 (ko) | 2015-10-27 |
GB2485082A (en) | 2012-05-02 |
JP2012532381A (ja) | 2012-12-13 |
CN102473091A (zh) | 2012-05-23 |
KR20120106696A (ko) | 2012-09-26 |
CN102473091B (zh) | 2014-09-17 |
US8195917B2 (en) | 2012-06-05 |
GB2485082B (en) | 2015-08-26 |
GB201200020D0 (en) | 2012-02-15 |
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