GB2451502A - Circuit for direct digital synthesis - Google Patents

Abstract

A circuit for direct digital synthesis comprises a phase generator (PGM) arranged for being fed with a phase generator input signal, a phase-to-amplitude converter (PACM) arranged for being fed with a phase from the phase generator and for generating a carrier wave output, whereby the phase generator input signal, the phase from the phase generator and the carrier wave output are vector signals. The elements of the vector signals represent a polyphase decomposition of the vector signals.

Description

CIRCUIT FOR DIRECT DIGITAL SYNTHESIS

Field of the invention

[0001] The present invention relates to the field of circuits for implementing direct digital synthesis.

State of the art [0002] Direct Digital Synthesis (DDS) is a flexible technique to generate carrier wave (CW) signals. A CW signal is generated according to Equation 1: cw(k1) cos(2irp(k1)) + j sin(2irp(k1)) (Eq. 1) The signal p(kT1) represents the phase of the CW signal at time instant kT1, with k an integer number and T1 the sample period. Equation 2 shows the relationship between T1 and the frequency Fclk of the digital processing clock Cik.

Fc,k_1/TI (Eq.2) [0003] The well-known DDS architecture as shown in Fig.l includes a phase generator (PG1) and a phase-to-amplitude converter (PAd). The phase-to-amplitude converter generates the cw(kT1) output signal, given a phase input signal p(kT1). A typical implementation (as shown in Fiy.2) employs a lookup table (RaM or synthesized logic) with the phase p(kT1) applied to its address input.

The lookup table output is two sets of q polynomial coefficients [co c1 c2... cqil and [so s1 2 *.. q1] . These two coefficient sets are inputs to a (ql)t order piecewise polynomial interpolator (e.g. Taylor, spline, ...) to compute the actual cosine and sine output signals. The scaling factor 2n in Eq.1 is implicitly taken into account in the phase-to-amplitude lookup table.

[0004] The internal structure of the phase generator (Fig.3) is a cascade of N integrator stages, each with the same transfer function H(z)=HN(z). . .=H2(z)=H1(z). This integrator transfer function H(z) is shown in Eq.3.

H(z)= S:(z) Z with i=0,...,N-l (Eq.3) D1(z) 1-z The input tuning words d1(kT1) (i = 1, ..., N) and (optionally) the enable signals Hold1(kT1) control the phase trajectory via the control port, e.g. to induce frequency and phase hops, frequency hops, frequency sweeps, modulation etc. Although the cw(kT1) signal may wiggle fast and mandate a high sample rate 1/T1, the tuning words d1(kT1) may have relatively low bandwidths that can be accommodated with a shared control port. With the 2n factor being taken into account in the phase-to-amplitude converter, all dj(kT1), s1(kT1), p(kT1) signals are in the range [-0.5, 0.5[. The optional Hold1(kT1) signals provide control to either let computation proceed or hold the different stage states. Equation 4 shows the relationship between the z-transforms of the tuning word inputs D (z) and the phase output P(z). N( -i

2 D,(z) 01-z) (Eq.4) [0005] The algorithm described so far is a one-phase DDS with Nth order phase trajectory. One-phase refers to the number of CW samples computed per digital clock cycle.

In this case all signals cw(kT1), d1(kT1), s1(kT1) and p(kT1) are scalar signals, i.e. they carry one value per digital clock cycle. Equation 5 shows the first Nyquist band for complex CW signals having frequency F0 generated with a one-phase DDS F E[-.�=-&[ (Eq. 5) ° 2 2 The same size frequency span is available if other Nyquist bands are of interest.

[0006) In some applications however the required F0 (in absolute frequency) drives the required digital clock frequency Fclk out of the implementation sweet-spot in terms of area and/or power Consumption, and possibly even into a non-implementable digital design. This problem can be overcome by computing multiple (M) signals per digital clock cycle. Equation 6 shows the first Nyquist band for complex CW signals generated with an N-phase DDS.

F E[_M. M.Fc!k[ (Eq. 6) out 2 2 The same size frequency span is available if other Nyquist bands are of interest.

[0007] Patent document US6587863 proposes a DDS structure wherein N interleaved one-phase DDS engines are used each running at a same clock rate. The appropriate phase offsets d0 are applied between the M different DDS engines.

[0008] An alternative solution to the above-mentioned problem is to use a one-phase phase generator that computes a single scalar phase signal p(kT1). This scalar p(kT1) signal is then piecewise linear interpolated with a factor of N. The resulting M phase approximations are concurrently applied to M phase-to-amplitude converters.

[0009] Both approaches have two drawbacks. Although working well for simple linear phase trajectory (i.e. constant frequency), they are both unable to perfectly track the phase trajectory for orders higher than 1, e.g. in swept frequency applications. This introduces spurs and noise in the frequency domain. The higher the M factor and the higher the phase trajectory order N, the more severe the approximation error and spurs.

Secondly, they are unable to apply any control word d2 at the same time resolution as the CW sample rate. For instance, with these schemes for M-phase DDS, M samples are computed per clock cycle. However, it is not possible to apply frequency hops or modulation at a time resolution finer than MT1. The larger the N factor, the greater this loss of accuracy is.

Aims of the invention [0010] The present invention aims to provide a circuit for direct digital synthesis that allows generating carrier wave signals in an increased output frequency range and whereby the drawbacks of the prior art solutions are avoided.

Summary of the invention

[0011] The present invention relates to a circuit for direct digital synthesis comprising a phase generator arranged for being fed with a phase generator input signal, a phase-to-amplitude converter arranged for being fed with a phase from the phase generator and for generating a carrier wave output, whereby the phase generator input signal, the phase from the phase generator and the carrier wave output are vector signals. The elements of the vector signals represent a polyphase decomposition of the vector signals.

[0012] In a preferred embodiment the phase generator comprises a plurality of vector adders. Advantageously, the phase generator comprises a plurality of integrators. The phase generator may further comprise a plurality of carry-save adder trees. In a preferred embodiment the phase generator is made reconfigurable such that it can deal with multiple CW signals.

[0013] Preferably the elements of the vector signal representing said phase have a value between -0.5 and 0.5.

(0014] In an advantageous embodiment the phase generator is further arranged for receiving a control signal.

[0015] In another aspect the invention relates to an integrated circuit comprising the circuit as previously described.

Short description of the drawings

[0016] Fig. 1 represents a generally known DDS architecture.

(0017] Fig. 2 represents a phase-to-amplitude converter.

[0018] Fig. 3 represents a phase generator for an Nt order phase trajectory.

[0019] Fig. 4 represents an M-phase DDS architecture.

[0020] Fig. 5 represents an M-phase phase generator.

[0021] Fig. 6 represents an example phase generator stage for N=3.

[0022] Fig. 7 represents a modular DDS architecture.

Detailed description of the invention

[0023] A polyphase decomposition of a discrete-time signal x(kT1) into N phases can be performed as shown in Equation 7 x(kT1)= x"(k7) (Eq. 7) whereby the addends x'(kT1) as defined in Eq.8 are called the polyphase components x"(k7) = x(kT,).>2 S(k -nM -A) (Eq. 8) The z-domain equivalent of Equation 7 is given in Eq.9 X(z)=zX(zM) (Eq.9) Its addends as shown in Equation 10 are called the polyphase components of the z-transform.

XiJ>l(z)__zxA(zM) (Eq. 10) The signals x2(k.A4TI) in Equation 11 are the time-shifted and down-sampled polyphase components of x(kT1). They are referred to as normalized polyphase components.

x2(k.M7) = x((kM + 2)7)= xr((kM� 2)7') (Eq. 1].) Note that often normalized polyphase components are simply referred to as polyphase components (see e.g. Sample Conversion in Software Configurable Radios', T.Hentschel, pp.55-58, 2002, Artech House). After decomposition of the original signal x(kT1) into its normalized polyphase components x2(k.M7), computations can be performed at a reduced F'1k, as can be seen in Eq.12. 1 1

FCIk_MT_-(Eq.12)

I M

[0024] The recomposition from (normalized) polyphase representation into the underlying signal reflects the behaviour of a rotating switch (commutator) . For example, after computation of the normalized polyphase components of a CW signal, a commutator composes the actual CW signal cw(kT1) as the last step before digital-to-analogue conversion, see equation 13.

cw(kY) CW:)m M) (k7) = CW()(pjj M) .M7) (Eq. 13) [0025] The M normalized polyphase components of a signal x(kT1) can be combined in a time domain vector signal as shown in Equation 14, wherein TM equals M.T1.

x(k.TM)_-[xo(k.TM) xl(k.TM) ... xI(k.TM)]T (Eq. 14) Equation 15 shows the equivalent z-domain vector.

X(z)=[X0(z) X1(z) ... (Eq.15) [0026] A scalar system with transfer function H(z) relates a scalar input signal X(z) to a scalar output signal Y(z) as shown in Equation (16).

Y(z) = H(z)X(z) (Eq. 16) This system can be raised into an equivalent system with transfer matrix H(z) with input and output normalized polyphase component vectors, as shown in Equation (17) Y(z)=H(z)X(z) (Eq.l7) The polyphase component vectors in Eq.17 describe exactly the same underlying signal as the scalar signals in Eq. 16.

The raised transfer matrix H(z) of a linear time-invariant system is a pseudo-circulant matrix of the form in Eq. 18 110(z) zHNI(z) zHN_2(z) ... zH1(z) 111(z) 110(z) zHNI(z) ... zH2(z) H(z)= (Eq.18) HMI(z) HM2(z) HM3(z) ... 110(z) The HA(z) hereby represent the z-transforms of the normalized polyphase components of H(z).

[0027] Polyphase representation and filtering as discussed above are generally known. In the present invention they are applied to a DDS phase generator.

A polyphase phase-to-amplitude converter computes the normalized polyphase components of the CW signal. This polyphase implementation allows computation at a lower clock rate (see Eq.l2). If desired, e.g. before digital-to-analog conversion, the actual CW signal can be constructed with a commutator (Eq.13).

[0028] The N-phase DDS architecture (as shown in Fig.4) is similar to the one-phase architecture (in Fig.l), except that interconnects are now Mxl normalized poly-phase vector signals (bold arrows). N-Phase phase-to-amplitude converter (PACM) and phase generator (PGM) are discussed more in detail below.

[0029] A phase-to-amplitude converter has no functional state, i.e. no functional memory elements.

Hence, in an N-phase phase-to-amplitude converter, each cw(k.TM) polyphase component of the vector cw is computed from its corresponding phase input p,(k.TM) solely, as can be seen in Equation 19.

-J22rp1(kT) cw(p(kTM))= ... (Eq.19) eJ2MTM) Hence, the N-Phase PAC is a set of M one-phase phase-to-amplitude instances.

[0030] The N-phase phase generator with Nt order phase trajectory (Fig.5) is the vector equivalent of Fig.3.

Bold arrows indicate where scalar signals are replaced with normalized polyphase vector signals. Operators (integrators H(z) and adders) are replaced with their matrix equivalent.

Equation 20 is the vector equivalent of Eq.4.

P(z) = H'(z)D,(z) (Eq. 20) Equation 21 shows the normalized polyphase components for the integrator transfer function H(z) (Eq.3) z-1 1 (Eq. 21) z-1 Substitution of Equations (21) into (18) yields Eq.22.

1 1 1 1 z-1 z-1 z-1 z-1 z I 1 1 z-1 z-1 z-1 z-1 H(z)= . . . . (Eq.22) z z z I z-1 z-1 z-1 z-1 H(z) can be decomposed as shown in Equation 23.

H(z) B(z).A(z) with z_I z_l z_I... z_I 1 z' z1. z1 B(z)= 1 1 1.: 1 *** 0 1-z 1 *** 0 1-z A(z)= o o o 1 (Eq.23) 1-z' The logic in Equation 23 runs exclusively at the reduced clock frequency FM = 1/TM. Computational resources are: * A(z) with only M scalar integrators 1/(1-z'), one for each input signal component.

* B(z) with only unity and z' elements, having small or no implementation cost. The dot-products of B(z) rows with A(z) outputs can be implemented very efficiently with carry-save adder trees.

Fig.6 shows an example phase generator stage for M=3.

[0031] With a small amount of extra programmability in the B(z) matrix, the hardware for an M-Phase DDS implementation can be made "reconfigurable" to support multiple Mn-phase DDS engines, constrained by MJ�=M (Eq.24) whereby L is the number of DDS engines. Or alternatively, multiple DDS engines can be merged into a higher sample-rate DDS engine. Equation 25 establishes the relationship between input and output of a HL(z) transfer matrix for L phase trajectories.

So,, (z) Do,,+1 (z) HL(z) ... (Eq.25) SL-I,,(Z) DL-I,i+(z) D,1+i(z) and S,(z) are the signal vectors related to the th phase trajectory. Equation (26) shows what HL(z) looks like. The only difference with the transfer matrix in Equation 23 is that the matrix elements indicated with [0] are masked to zero. A matrix B(z) provided with programmable elements enables the trade-off of number of CW signals with sample rate of each individual CW signal.

z_l z_I... z_l I z1.. Z [0] [0] 1 1-z' -l 1 1...z 1 HL(z)= [oJ [...] [0] . z_I zI... z_I... ...

[0] [0] III.. ° ° 1 I I...

(Eq. 26) (0032] As an example, hardware supporting the phase trajectory for 48-phase DDS, plus a little programmability to zero-out matrix elements where required as shown above, can be used for 48-phase]JDS, two concurrent 24-phase DDS, one 32-phase DIDS, one 40- phase DDS etc.... Fig.7 shows how this works for the three-phase DDS. With the addition of only the gating (AND gates), the hardware can serve either as -one three-phase DDS, -concurrently: one two-phase DIDS and one one-phase DDS, -three concurrent one-phase DDS engines.

Claims (8)

1. A circuit for direct digital synthesis comprising a phase generator (PGM) arranged for being fed with a phase generator input signal, a phase-to-amplitude converter (PACM) arranged for being fed with a phase from said phase generator and for generating a carrier wave output, whereby said phase generator input signal, said phase from said phase generator and said carrier wave output are vector signals, whereby the elements of said vector signals represent a polyphase decomposition of said vector signals.

2. The circuit of claim 1, whereby said phase generator (PGM) comprises a plurality of vector adders.

3. The circuit of any of claims 1 or 2, wherein said phase generator (PGM) comprises a plurality of integrators.

4. The circuit of any of claims 1 to 3, wherein said phase generator comprises a plurality of carry-save adder trees.

5. The circuit of any of the previous claims, wherein said phase generator is reconfigurable.

6. The circuit of any of the previous claims, whereby the elements of the vector signal representing said phase have a value between -0.5 and 0.5.

7. The circuit of any of the previous claims, whereby said phase generator is further arranged for receiving a control signal.

8. An integrated circuit comprising the circuit as in any of the previous claims.