GB2344237A - Digital control of cross-over distortion in push-pull amplifiers - Google Patents

Abstract

Apparatus for controlling the output stage of a push-pull amplifier is described. Control is performed digitally which can pre-warp and shape an input waveform to take account of changing transfer characteristics of the analogue output stage(s). Shaping is applied to reduce crossover distortion and improve overall linearity of the amplifier. Feedback is continually applied by sampling, using a high resolution Analogue to Digital Converter (ADC) and monitoring the amplifier's output transfer characteristics. The digital means can also be employed to perform volume control and tonal control by implementing the appropriate digital filters. Output transistor bias and pre amplification are determined and performed by digital means, the output transistor input voltage being provided via a Digital to Analogue Converter (DAC) and a buffered low pass filter. This leads to a reduction in noisy analogue circuitry.

Description

2344237 DIGITAL CONTROL OF CLASS A, CLASS AB, CLASS B AND CLASS D

AMPLIFIER OUTPUT STAGES This invention relates to the digital control of the output stages used in class A, class AB, class B and class D power amplifiers.

One method of classifying amplifiers relates to the relationship between the input signal and the current flowing in the load circuit. For Class A amplifiers the current flows in the load for the whole period of the input signal cycle. Where the load current flows for more than one half cycle, but less than a full cycle of the input signal the amplifier is a Class AB. Class B amplifiers are typified by the load current flowing for less than one half cycle of the input waveform and Class C the current flows for less than one half cycle of the input signal.

Class AB, B and Class D amplifiers are more efficient than pure Class A amplifiers as a quiescent operating current is required even under zero output power conditions. Therefore, power is dissipated in the amplifier under no load conditions. To alleviate this problem Class AB and Class B amplifiers are employed in which the output transistors are biased to limit the quiescent current to either zero or a small fraction of the full output current.

However, Class AB and Class B amplifiers are subject to a form of distortion known as crossover distortion. This is illustrated in Figure 1. This problem occurs due to the non-linearity of transistor output characteristics and when in a push-pull configuration one transistor is turning off and the other transistor is turning on.

Figure 1 shows two output characteristics for a Class B push-pull output stage. The ideal straight line transfer characteristics is shown by line (B) where no cross over distortion is introduced when ideal transistors switch. Line (A) shows the transfer characteristic for a Class B or Class AB output stage which employs silicon junction transistors in which the output current is suddenly turned on with increasing input voltage. Negative feedback is employed to reduce the crossover distortion which attempts to make the transfer characteristic more linear as shown in Figure 1 (line b). However, at low signal levels more distortion is experienced as the output signal only traverses a limited swing of the output characteristic. This tends to provide the listener with a thin sound. To provide better linearisation, designers have previously increased the level of negative feedback. Unfortunately, this has the effect of reducing the load stability and transient response of such amplifiers.

Other factors contributing to crossover distortion and non-linear amplification are the different transfer characteristics of complementary NPN and PNP transistors.

Crossover distortion is worse at lower power levels where most listening is done. Crossover distortion tends to distort the output waveform by introducing dissonant seventh, ninth, eleventh and thirteenth harmonics which are audibly disturbing.

Initial attempts to overcome this problem included applying negative feedback between the output and the input of the amplifier to help linearise the transfer characteristics. This helped, but did not eradicate the problem. In fact, too much negative feedback can lead to a deterioration in load stability and the amplifier's transient response. Another way to improve the effects of crossover distortion is to employ power MOSFETs in the output stage as they have better linearity, have higher operating frequencies and do not suffer from stored charge effects. Figure 3 shows the dynamic mutual characteristics for both a bipolar transistor and a Power MOSFET. The latter problem limits turn off times in bipolar transistors. Another advantage of power MOSFETs is that they have a positive temperature coefficient at low currents, but a negative temperature coefficient at medium and high currents.

Other problems with conventional amplifiers are changes in operating conditions due to component ageing, changes in transfer characteristics due to temperature changes and providing extra circuitry to control problems of thermal runaway, output protection and transistor biasing and feedback. Other analogue pre-amplification stages are required to drive the push-pull output stage which can affect the overall performance of the amplifier.

According to the present invention there is provided amplification apparatus comprising a push-pull output stage using complementary Nchannel and Pchannel transistors or valves, digital processing means for providing varying degrees of bias voltages for the output stage transistors which is applied via analogue to digital converter, buffer and low pass filter means, the digital signal processing means performing pre-warping and shaping of the digital input signal, the shaping function being used to counteract the measured non linearity of the output transfer characteristics of each channel's output pushpull stage, the pre warping and shaping function being determined by constantly monitoring the amplifier output signal for each channel, a sampled version of which is fed back to the digital processing means via an analogue to digital converter (ADC) and buffer means, this feedback signal being a representation of the transfer characteristics of the amplification stages, digital to analogue converter (DAC) means to convert the shaped digital signal in to an analogue signal which is buffered and low pass filtered to remove quantization affects before being applied to the input of each transistor of the push-pull output stage, the digital processing means therefore controlling the two output stage transistors of each channel independently which also provides correct biasing and temperature compensation, the output level of each channel from the digital signal processing means also being determined by the value of the volume parameter.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:- Figure 1 shows the input - output stage characteristics for a typical transistor class B push-pull amplifier and how crossover distortion manifests itself in the output waveform; Figure 2 shows the resultant output characteristics of a push-pull stage when bias voltages are applied to the transistor inputs to reduce crossover distortion; Figure 3 shows the typical transfer characteristics of both a bipolar junction transistor and a power MOSFET; Figure 4 illustrates the input - output characteristics for a transistor and how pre warping and shaping an input signal can minimise crossover distortion; Figure 5 illustrates a logical block diagram of a digitally controlled amplifier showing several separate channels; Figure 6 shows a a channel output stage in more detail; Figure 7 shows how the feedback signal from several channels can be passed via an analogue switch to a single Analogue to Digital Converter (ADC); Figure 8 illustrates a modified channel output stage for use in Class D applications; Figures 9 (A) and 9 (B) shows respective flowcharts relating to the operation of the Figure 4 apparatus; and Figure 10 shows the a high level flowchart for implementing digital pulse width modulation.

Referring to the Figure 5, the digitally controlled amplification apparatus 10 includes several analogue output stages 20 each consisting of two complementary transistors 25 and 26. These transistors 25 and 26 can be bipolar or power MOSFETs. In fact, the output transistors 25 and 26 could be replaced by electronics valves if additional circuitry was used to provide heater voltages and output transformers for load matching. The transistors form a push-pull arrangement in which one transistor is conducting during the first half cycle and the other is conducting during the second half cycle. They can be some overlap in conduction in class AB configuration due to biasing. Each channel output stage 20 is connected to a corresponding loudspeaker 30. The positive terminal of which can be decoupled to the amplifier stage 20 via a decoupling capacitor 29. Resistors 27 provide current limiting.

To power the apparatus 10, various power supply voltages must be supplied to the apparatus 10. The outrut stages tend to have high voltage power supply requirements, but depend on the amplifier power rating. These power supply voltages are typically in the range of 40 - 100 Volts. The positive power supply 40 is connected to the N channel transistors 25 and the negative power supply 41 to the P channel transistors 26. In some amplifier configurations (not shown) the negative power supply 41 is zero Volts. Other power supply voltages are also requited, but not shown here, to power the other active components that form the apparatus 10. These are much lower voltages and all power supply lines are preferably derived from a stabilised power supply (not shown). Such a stabilised power supply would preferably be integrated into the amplifier apparatus 10.

As the apparatus 10 is based on digital circuitry and sampled signals, clocking signals 18a will be required. Several very stable clocks 18a of different frequencies will be required and can be generated from a crystal source and divided down as necessary. The system clock generator 18 provides this function.

The apparatus 10 can be controlled either by panel mounted control means 16 and or remote control means (not shown). The various settings are displayed say on a liquid crystal display (LCD) 17 when any changes to the setting is made by the user. The output audio level being set by the volume control 16. As the volume level will be an input parameter used by the digital signal processor means 11 this signal will be of a digital format. As will the other tone control parameters used to filter the input signals 14a and 15a. This can be set either digitally or by analogue means. The latter method requiring an Analogue to Digital Converter (ADC), not shown, to convert the analogue volume setting to a digital volume setting. Any volume, balance or tone control settings can be displayed on the display means, such as a liquid crystal display (LCD) 17.

As shown in Figure 5, the input to the amplifier is a digital signal 14a from one of several sources, for example a Compact Disc Player, a Digital Audio Tape (DAT) player, a Digital Video Disc, which is a representation of the desired analogue signal. Digital signals 14a are buffered first by the digital interface block 14. The digital signal could be a proprietary format, but would normally be a Sony Philips Digital Interface Format (SPDIF) and or conform to the IEC 958 encoded signals. Any analogue input signal 15a, for example from a tuner or cassette player, first being converted to a digital format using Analogue to Digital Converter (ADC) means 15. Of course, the greater the resolution of the Analogue to Digital Converter means 15, the better the representation of the input signal. Today's ADCs, such as Analog Device's AD 1879 can provide up to 20-bit resolution.

This digital signal 14a is read by the digital signal processing means 11 at the appropriate sampling rate. Stereo amplifiers use two channel, left and right.

However, surround sound systems use up to five separate channels. The current embodiment as illustrated in Figure 5 shows a block diagram of the digital amplifier apparatus 10 with several (n) channel output stages 20. The digital signal processing means 11 could sample digital signals 14a for several channels depending on the processing power of the digital processing means and the configuration of the amplification means. The digital signal processing means 11 could be a form of DSP device such as a Texas Instrument's TMS320C6x series or Analog Devices ADSP 21160 SHARC.

Other processing devices could also be used to implement the digital signal processing means such as standard microprocessors.

In a conventional analogue power amplifier, say a class AB amplifier, these output transistors 25 and 26 would be have circuitry to provide a bias current and circuitry to stabilise the transistor and prevent thermal runaway. Any analogue input signal would have to be buffered and pre-amplified before being input to the output stage transistors. To reduce the affects of crossover distortion a bias voltage is applied to the gate or base of the output transistors 25 and 26. This is illustrated in Figure 2.

One way to overcome the crossover distortion is to use digital signal processing means 11 to pre warp and shape the input signals 14a and 15a to counteract the measured crossover distortion at the output of each channel 20.

Figure 4 shows the actual and ideal input - output transfer characteristics for a N channel transistor 25. To prevent crossover distortion at the output, the transistor 25 can be operated in its linear region by apply a bias voltage. However, this method doesn't fully prevent crossover distortion due to the switching action of the two output transistors. To help reduce the crossover distortion to minimum, the input signal can be pre warped or shaped if it is calculated that the output voltage would fall in the non linear region of the transistor's transfer characteristic. For example, without pre warping the input signal 14a representing an input voltage of 7.5 Volts would produce an output current of 4 mA. However, this input voltage would be operating in the transistor's non linear region and distortion would occur in the output. To prevent this distortion, the digital signal processing means 11 can pre warp and shape the input signal 14a or 15a such that no crossover distortion occurs in the output. For example, as shown in Figure 5, the ideal output current for an input voltage of 7.5 volts would be 3 mA, but the actual output current would be 4mA. Therefore, to achieve this pre warping and shaping the digital signal processing means 11 applies an output signal equivalent to 7 Volts. The digital signal processing means 11 would perform this pre warping of the input signals 14a or 15a for signals that would fall into the transistor's non linear region. Two tables are shown in Figure 4. One shows the input - output transfer characteristics of an actual transistor and the other shows th ideal transfer characteristics where no crossover distortion occurs. Note, the figures shown for the actual transfer characteristic are artificial to illustrate the affects. This pre warping and shaping would be performed for each output channel 20. Of course, more pre warping and shaping would be required if the volume setting was low as more of the signal would be in the non linear region.

The amplification apparatus 10 could employ pure pre warping and shaping to eliminate crossover distortion at the output of each channel or use a combination of both bias voltage and pre warping and shaping. The bias voltage would be calculated by the digital signal processing means 11 based of the feedback signals 28a from each channel 20.

The digital input signal 14a is shaped or pre-warped for each channel 20 based on information (feedback signal 28a) fed back to the digital signal processing means 11 from the output stage of that particular channel. This feedback 28a signal is a sampled version of the output signal and is converted to a digital format using Digital to Analogue Converter (DAC) means 23, such as a Burr Brown PCM 1728 or PCM 1716 device. The feedback signal 28a can be current limited using a resistor 28 depending on the feedback configuration. This feedback signal 28a represents a version of the output signal after it has been converted to an analogue form and amplified by the output stage transistors 25 and 26. Any deviations to the signal from the original can then be monitored and compared to the original input signal. The output stage transfer characteristics vary with temperature, frequency of operation and transistor age. Short term changes to the transistor transfer characteristics will distort the input signal in a short time period during the operation of the amplifier 10. Therefore, the pre-warping or shaping function needs to continually adjust to take account of these continuing transfer characteristic variations. This is achieved by constantly monitoring the output signals 28a for each channel and feeding a digital version for each channel back to the digital signal processing means 11. The transfer characteristics for N-channel and P-channel transistors also vary so there would be different distortion at the output during a single cycle of a waveform. The pre warping and shaping function performed by the digital signal processing means 11 could account for these variations and shape the input signal 14a or 15a accordingly to eliminate this form of distortion.

To establish the initial pre-warping or shaping function, the digital signal processing means 11 performs a measuring routine in which stepped voltages are applied to both output stage transistors 25 and 26 and the output response voltage 28a is sampled and fed back to the digital signal processing means 11. This process is performed for each channel 20 and the routine is performed before any input signal is applied to the amplifier apparatus 10. This measuring routine allows the digital signal processing means 11 to determine the overall input-output characteristics for each channel 20 of the amplifier apparatus 10. It also allows the digital signal processing means 11 to apply the necessary bias voltages to the output transistors 25 and 26 to ensure optimum operation. By constantly monitoring the output characteristics the digital signal processing means 11 can also control the transistors 25 and 26 to prevent thermal runaway. Transistor heating effects also modify the transfer characteristics which can be compensated for by the pre-warping or shaping the input signal accordingly.

The digital signal processing means 11 uses several peripheral components to source and sink digital data. These peripheral components are connected to the digital signal processing means 11 via a bi-directional tri-state data bus 11e, an address bus 11d and control signals 11f which perform read, write and chip select functions. Programs to perform the various computational processes are stored in non-volatile memory, such as Flash EPROM 12. The program memory 12 being connected to the digital signal processing means 11 via an instruction address bus 11a, data bus 11c. Chip select and read signals are also provided 11 b. Data storage for processing the channel data is provided by volatile memory 12a, such as SDRAM, and is connected to the digital signal processing means 11 via the data bus 11 d and address bus 11 e. Chip select, read and write and relevant clock signals 11 f are provided to access the data memory 12a. The width, depth, speed and type of memory being dependent on the application and functions required. It should be noted that different digital signal processing means 11 have different architectures and may or may not have separate buses for instruction memory 12 and data memory 12a.

Figure 5 shows a high level block diagram of the apparatus 10 using a single channel output stage 20. The pre-warped or shaped digital data output from the digital signal processor 11 is transferred to either one of the Digital to Analogue Converters (DACs) 21 depending on the phase of the input signal. The data is output at such a rate as to minimise aliasing affects and in accordance with Shannon's sampling criteria. The digital data word is converted to an analogue form by the Digital to Analogue Converter 21. If not provided by the Digital to Analogue Converters, buffering (which can take form of either discrete components and or use operational amplifier devices) and low pass filtering 22 is performed to remove quantization affects from the analogue waveform e.g. smooth the signal. This signal is then passed to the input (base or gate depending on transistor type) of the output transistors 25 and 26. As this is a closed loop system the digital signal processing means 11 can monitor the affects of signal distortion due to the output stage and pre amplification and apply the necessary shaping to the input signals to linearise the output signal. Providing separate and independent control of each output transistor allows greater flexibility. This allows each transistor to be controlled independently and provides smoother switching at the crossover point when one transistor needs to be switched off and the other switched on.

The advantages of using a digital signal processing method to control the output stage of a push-pull amplifier are-- individual channel input signals can be accurately pre-warped or shaped in accordance with changing transfer characteristics of the pre amplifier (buffer 22) and output stages 25 and 26, this includes taking account of different transfer characteristics for N-channel and P-channel transistors 25 and 26; more efficient and accurate switching between the two push-pull transistors 25 and 26 is provided; it reduces the need for noisy analogue circuitry used for pre amplification, biasing and temperature stabilisation employed in analogue power amplifiers. This in turn reduces the analogue complexity, the digital signal processor 11 can be used to perform other functions such as tone control by implementing digital filters, this configuration can be used to implement more power efficient Class D amplifiers, digital signals 14a from digital sources, such as compact disc (CD) players and Digital Audio Tape (DAT) players can be processed directly by the digital signal processor 11, the digital signal processor 11 can also monitor and provide temperature stabilisation, when no input signal is detected by the digital signal processing means 11 the output to the transistors 25 and 26 of the output stage can be reduced to ensure they are turned off and are not passing any load current. This reduces power dissipation. In conventional analogue class AB amplifiers the output transistors are constantly biased in such a way that the quiescent current is zero or substantially less than that used at full power output. However, it is this that leads to cross over distortion.

and the closed system is self adjusting based on the determination of the overall transfer characteristics of the output stage by the digital signal processor 11.

Figures 9 (A) and 9(B) are a flowchart illustrating the high level operation of Figure 5 apparatus. As shown in Figure 9(A), on power up the apparatus performs a reset function (step Sl) and initialises the appropriate internal registers. For example, the number of channels is set (X). To ensure the apparatus is operating correctly, several digital devices, such as the digital signal processing means 11 may perform Built In Self Test (BIST functions) as shown in step S2. When complete a check is carried to determine if the BIST functions have passed or failed (step S3). If they have failed an error message is displayed (step S4). However, if the BIST tests pass the apparatus proceeds to the next stage. Here, the digital signal processing means 11 performs the transfer characteristic routine for each output channel and then turns off the output transistors (step S5). Based on the feedback data 28a from each channel the digital signal processing means 11 calculates the pre warping functions and bias voltages for each channel output stage 20 (step S6). This routine must be perform at least once at apparatus power on and before any source data signals are processed. The apparatus is now ready for use.

The digital signal processing means now checks to see if source data is available (step S7). This could be achieved in one of several ways depending on the system. For example, the process could be initiated via an interrupt, polling and or the use of interface flow control signals, such as handshake signals. It is important to note that in apparatus such as this the digital signal processing means 11 could be performing several parallel tasks and could also be interrupted at any time to perform new tasks. For example, the user may make changes to the volume and tone setting or even select a new source of data. These parallel and asynchronous events are represented by the step S10. If no source data is available the digital signal processing means 11 performs a time-out (step S8) and effectively does into a sleep mode until triggered by the arrival of source data.

When the digital signal processing means 11 detects that source data is available (step S7) at any of the source interfaces 14 it first reads the source input, volume and tone control settings 16 as shown in step S9 and starts to read the source data samples for the various channels (step S1 1). To perform digital filtering functions such as Infinite Impulse Response (11R) and Finite Impulse Response (FIR) operations several data samples must be used. Therefore, the digital signal processing means 11 check to make sure enough data samples are read for the corresponding channel (step S12). If not, more source data samples are read. Once the correct number of source data samples have been read for that particular channel the digital signal processing means processes them as shown in step S13. The various signal processing routines depend on the user settings, but will include digital filtering to implement the desired tonal filtering. For example, implement low pass filtering, bandpass filtering and high pass filtering to reflect the settings of the treble and bass parameters 16. It will also include the pre warping of the source signal based on the volume setting and feedback information 28a form the channel output stage 20.

The processed signal is now output via the data bus 11 e and written into the corresponding digital to analogue converter 21 for that channel (step S14). The digital signal processing means 11 then reads and store the feedback signal 28a (step S15) via the resistor 28, the buffer 24 and the digital to analogue converter 23. Based on the feedback data 28a the digital signal processing means 11 then calculates the transfer characteristic for that channel and up dates the channel profile (step S16). By continually monitoring the transfer characteristics of the output stage transistors the digital signal processing means 11 can pre warp and shape the input signals 14a to ensure crossover distortion and other non linear amplifications affects are minimised and the amplified output signal for each channel is as linear as possible.

Step 17 in used to check if the source data for each output channel has been processed and output to the corresponding digital to analogue converters 21. If not, the channel number is incremented (step S1 8) and steps S1 1 to S1 6 repeated. When all channels have been processed for that particular set of channel samples, the channel number N is reset to 0 and the process return to step S7 ( point B in Figures 9(A) and 9(B).

In a second embodiment, the feedback signals 28a from the various channel output stages 20 can be fed back to the digital signal processing means 11 via a single Analogue to Digital Converter 23. This would reduce the cost of having an analogue to digital converter 23 and buffer circuit 24 for each stage. To achieve this, each feedback signal 28a, and current limited by resistors 51, are connected to one of the inputs of an analogue switch 50. Selection of the various feedback signals 28a for sampling by the analogue to digital converter 23 is controlled by the digital signal processing means 11 which uses address decoding 13, data bus 11 e and a read control signal 11 f to select the various channels 28a. Figure 6 shows a method of implementing the 'de-multiplexing' of the analogue feedback signals 28a for sampling by a single analogue to digital converter 23. Buffering 24 can also be provided depending on the type of analogue to digital converter 23 used.

Figure 8 illustrates the use of the apparatus to implement a Class D amplifier. In this further embodiment, any digital input signal 14a needs to be converted to a pulse width modulated signal before being applied to the output stage transistors 25 and 26 for the corresponding channel. To achieve this, the digital signal processing means 11 needs to convert the digital input signal 14a to a pulse width modulated format. In theanalogue world, a PWM signal is generated using a high-gain comparator. The analogue input signal is compared to a sawtooth waveform derived from a very stable source. The width of the generated pulses are directly proportional to the level of the input analogue waveform.

In Figure 8, the digital signal processing means 11 performs the digital pulse width modulation for each channel as outlined in flowchart of Figure 10. Of course, this only represent one way of implementing the digital pulse width modulation transformation. Engineers familiar with the art may wish to implement the function in different ways depending on the configuration of the apparatus means 10. The pulse width modulated signal is applied to the digital to analogue converters 21 via the data bus 11 e. Control signals 11 f and 13a are also used to write the data to the correct destination register and or device. The address being decoded by the address decoder 13 from the address output 11 d from the digital signal processing means 11. The voltage swing of the pulse width modulated signal can be determined by the digital signal processing means 11 outputting various digital values for the positive and negative values of the pulse width modulated signal. To control the volume of each channel the pulse width modulated signal must vary in voltage swing. This can be achieved by the digital signal processing means 11 outputting various digital values for the positive and negative values of the pulse width modulated signal and or by the digital signal processing means 11 setting the gain of the programmable gain amplifiers 22. The gain of the programmable gain amplifiers is set via the data bus 11e using the appropriate write and address decode signals 1 lf and 13a respectively. The output transistors 25 and 26 turned on in accordance with the amplitude of the voltage swing of the pulse width modulated signal. The output signal is then passed through low pass filter which is used to recover the true analogue waveform. This signal is than passed to the connected loudspeaker 30. This is repeated for each channel 20 used in the apparatus 10. To monitor and calculate distortion levels at the output of each channel, the digitalsignal processing means 11 samples a digital version of the output signal. This is achieved by passing a fraction of the output signal to an analogue to digital converter 23 via a buffer 24 and current limiting resistor 28.

The flowchart of Figure 10 describes a way to generate a pulse width modulated signal for a digital input signal. This is only described for a single channel, but can be applied repeatedly for each output channel.

In step S20 the parameter T is reset to the value 0 and the digital signal processing means 11 outputs a value corresponding to +V. The parameter T represent a count value which is incremented periodically by the digital signal processing means 11 as shown in step S21. The waveform produced by counter T is a digital sawtooth waveform who's frequency should be in accordance with standard sampling theory, that is, be at least twice the highest frequency of the source data signal. The resolution of each step or increment should also be graded appropriately to ensure there is no aliasing affects in the channel output. At step S22 the value of T is compared to that of the digital input signal 14a. If the value is equal to or greater than the value of T the procedure moves on to step S24 where the output voltage is set to either OV or -V by the digital signal processing means. To ensure the period of the digital sawtooth is the same the value of T is incremented (step S25 and step 26) until the value reaches its maximum. On doing so the value of T is reset to zero and the procedure repeats as one cycle of the digital sawtooth has been completed.

However, if at step S22 the value of the source signal 14a is less than the value of T the procedure moves on to step S23 where a check is made to determine if T has reached its maximum value. If it as then th procedure moves on to step S20. If not, then the procedure moves onto step S21. Of course, during the operation of this procedure the digital signal processing means 11 can be interrupted to perform asynchronous routines. These events are various depending on the apparatus mode and operation and are defined by step S27.

Claims (14)

1. Amplification apparatus comprising a push-pull output stage using complementary N-channel and P-channel transistors or valves, digital processing means for providing varying degrees of bias voltages for the output stage transistors which is applied via analogue to digital converter, buffer and low pass filter means, the digital signal processing means performing pre-warping and shaping of the digital input signal, the shaping function being used to counteract the measured non linearity of the output transfer characteristics of each channel's output push-pull stage, the pre warping and shaping function being determined by constantly monitoring the amplifier output signal for each channel, a sampled version of which is fed back to the digital processing means via an analogue to digital converter (ADC) and buffer means, this feedback signal being a representation of the transfer characteristics of the amplification stages, digital to analogue converter (DAC) means to convert the shaped digital signal in to an analogue signal which is buffered and low pass filtered to remove quantization affects before being applied to the input of each transistor of the push-pull output stage, the digital processing means therefore controlling the two output stage transistors of each channel independently which also provides correct biasing and temperature compensation, the output level of each channel from the digital signal processing means also being determined by the value of the volume parameter.

2. Apparatus as claimed in claim 1, wherein the amplification means is provided for more than one input and more than one output signal channel.

3. Apparatus as claimed in claim 1 or claim 2, wherein the output stage pushpull transistors are bipolar junction transistors of the same type or separate N-channel and P-channel transistors.

4. Apparatus as claimed in claim 1 or claim 2, wherein the output stage pushpull transistors are field effect transistors or power MOSFET transistors.

5. Apparatus as claimed in any proceeding claim, wherein the output stages are operated in Class D mode and the digital signal processing means converts any input signal input a pulse width modulated signal for each output channel.

6. Apparatus as claimed in any preceding claim in which any of the separate digital and analogue functions are integrated onto the same integrated circuit device to reduce the device count, reduce distortion and increase signal to noise ratios.

7. Apparatus as claimed in claims 2 to 6, wherein the feedback signal from the various output stages are first passed through an analogue switch and sampled by a single Analogue to Digital Converter (ADC), selection of the various feedback signals being controlled by the digital signal processor means.

8. Apparatus as claimed in any proceeding claim, wherein digital signal processing means performs a measuring routine at start up or during periods of no input signal to determine the output stage transfer characteristics for each push-pull output amplifier stage.

9. Apparatus as claimed in any proceeding claim, wherein the digital signal processing means turns off both the output transistors or valves when no input signal is detected to reduce power dissipation in idle mode.

10. Apparatus as claimed in any proceeding claim, wherein discrete components are used to form the low pass filter buffers rather than use operational amplifiers.

11. Apparatus as claimed in any proceeding claim, wherein the digital signal processing means can be formed from more than one signal processing devices or be a Digital Signal Processor (DSP), a microprocessor, a microcontroller, Reduced Instruction Set Computer (RISC), a Complex Instruction Set Computer (CISC) or any combination of these devices.

12. Apparatus as claimed in any proceeding claim, wherein the digital signal processing means implements digital filters to perform spectral shaping of the input signal based on the setting of treble, bass or other tone controls.

13. Apparatus as claimed in any proceeding claim, wherein power supply means are integrated into the amplifier apparatus.

14. Digitally controlled amplification apparatus as described herein with reference to Figures I - 10 of the accompanying drawings.