GB2332794A

GB2332794A - An optically clocked IC using a PLL clock frequency multiplier

Info

Publication number: GB2332794A
Application number: GB9727282A
Authority: GB
Inventors: William Eric Corr
Original assignee: LSI Logic Corp
Current assignee: LSI Corp
Priority date: 1997-12-23
Filing date: 1997-12-23
Publication date: 1999-06-30
Anticipated expiration: 2017-12-23
Also published as: GB9727282D0; GB2332794B

Abstract

An integrated circuit package 12 comprises an IC 14a and an LED 18 or laser diode for communicating an optical clock signal to clock regenerators 22 on the IC. Each regenerator includes a photodiode or phototransistor for converting the optical clock signal to an electronic clock signal. The optical clock has very low skew. At least one clock regenerator comprises a phase-locked-loop (figure 3) for generating a clock signal having a higher frequency than the optical clock signal, but which is synchronised to the optical signal to maintain a correct timing relationship with the optical signal. This allows clock signals to be generated which are too high in frequency for optical distribution using normal photoelectric devices. The emitter 18 may be carried on the IC, or it may be positioned to one side of the IC or above it (figure 1). The IC may be mounted directly on a circuit board.

Description

OPTICALLY CLOCKED INTEGRATED CIRCUIT The present invention relates to an integrated circuit using an optical signal to distribute a clock signal over an integrated circuit die, for example, as described in copending UK patent application no. 9712177.6 entitled Low Skew Distribution for Integrated Circuits.

The concept of distributing a clock signal in optical form is very promising, because it can avoid the problems of capacitive coupling and other signal interference encountered with traditional interconnect wires, and enable signals to be distributed with minimal signal skew. The speed of signal propagation is limited only by the speed of light (and the switching speed of the circuit components used to produce and receive the optical signals, which is predictable). For example, for a 15mm die, the attainable skew could be as small as about 50ps. This compares very favourably with the minimum of about 400ps which is attainable with conventional distribution wires. It is expected that future technologies will require a skew of less than about 200ps, which will be very difficult to achieve using conventional wire techniques.

Moreover, an optical signal can be used to distribute a clock signal to different parts of the integrated circuit die, without the same routing and design constraints as those associated with distribution wires. This can provide the die designer with greater flexibility of design, and allow circuits to be arranged on the die in relative positions not hitherto regarded as practical.

Broadly speaking, one aspect of the present invention is to distribute a clock signal across and integrated circuit as an optical signal, and to generate at an optical receiver, a second clock signal synchronised to the optical signal but having a different frequency from the optical signal.

Preferably, the ratio of the optical frequency over the second clock signal is 1/M or M/1, where M is an integer. Preferably the second clock frequency is higher than the optical clock frequency.

In devising the present invention, it was appreciated that although optical distribution can achieve very low skew levels, the photoelectric devices will have a cut off frequency above which the optical signal will not be faithfully reproduced at the optical receivers. This will occur when the period of the optical clock is reduced towards the minimum time window for generation of a photoelectric effect in the particular device. The cut off frequency may depend on the characteristics of each photoelectric device, as well as other parameters such as operating voltage and current.

The present invention enables a second clock frequency to be produced which is itself synchronised to the optical clock (and hence achieves the same low skew), but may be of a frequency too high for optical distribution.

In a preferred form, the second frequency is generated by means of a phase locked loop circuit.

The optical signal may be produced by an optical emitter carried on the die, or carried within the integrated circuit package containing the die, or mounted externally to provide an optical input to the package. The optical signal may illuminate substantially an entire surface of the die, or one or more predetermined areas of the die. Opaque masks may be used to mask areas of the die not intended to receive optical radiation (for example, to reduce unwanted photoelectric effects). If desired an optical guide (i.e. a light guide) may be provided to define predetermined optical paths for the optical signal. Such a guide may be provided by translucent material which can diffuse the light to achieve excellent omni-directional illumination, and avoid shadow effects.

More than one emitter may be used to generate a larger magnitude optical signal, or a plurality of different optical signals.

The or each optical signal may be directly equivalent to the signal it represn so that a digital pulse (e.g. a clock pulse) is represented by an optical pUI.

Alternatively, the optical signals may be encoded, for example by modulation.

The optical signal may represent a single signal, or it may represent a plurality of signals. For example, the plurality of signals may be multiplexed, or have different characteristic carrier or modulation frequencies, or be represented by different radiation wavelengths, to enable individual signals to be separated either optically or electronically.

In a preferred embodiment, the optical signals are clock signals, and are distributed across the die and used to clock a plurality of circuit elements, for example, data storage registers. Each element may have, or be associated with, its own optical receiver. Alternatively pluralities of elements may be grouped together and fed from a respective optical receiver for the group. In this way, the optical technique is used to distribute signals on a die-scale, and local wires are then used to distribute the signals to local circuits.

An embodiment of the invention is now described by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is schematic section through an integrated circuit package; Fig. 2 is a schematic section along the line II-II of Fig. 1; and Fig. 3 is a schematic circuit diagram of a receiver circuit element implemented on the integrated circuit die.

Referring to Figs. 1 and 2, an integrated circuit device 10 consists of a package base 12 on which is carried an integrated circuit die 14. In this embodiment, the die 14 is based on a silicon substrate, but other embodiments may use different semiconductor materials. In Fig. 1, the conventional package terminal pins or balls, and the connections between the pins (or balls) and the die, have been omitted for the sake of clarity; these features are well known to the skilled man. Pins are denoted schematically in Fig. 2 by numeral 16.

The device 10 includes an optical emitter 18 mounted on one side of, and slightly above, the upper surface 14a of the die 14. The emitter 18 is supported by the package base 12 and is attached thereto, for example, by adhesive. The die 14 and the emitter 18 are covered by translucent encapsulation material 20 to allow light emitted by the emitter 18 to fall on the die surface 14a. The emitter 18 is driven by an external signal applied through one or more respective "clock input" pins 16a of the device 10.

Referring especially to Fig. 2, the die 14 includes a plurality of circuit elements 22, two of which are illustrated. The size of the elements is greatly exaggerated in Fig. 2 for the sake of clarity; this figure is purely schematic. Each circuit element 22 includes an optical receiver, in the form a phototransistor or photodiode 24, positioned in the die 14 to receive optical radiation through the upper face 14a. The light signals are used as clock synchronisation signals from which the circuit elements 22 can generate their own local clocks.

Figure 3 illustrates an example of a circuit element 22. The output from the photodiode 24 is coupled to the input of a conditioning circuit 26, which may typically include an amplifier 26a and a thresholding circuit 26b for conditioning the optically received signal. The output from the conditioning circuit 26 represents a usable clock synchronisation signal, and is fed as an input to a phase lock loop circuit consisting of a multiplier (phase comparator) 28, a loop filter 30, a voltage controlled oscillator (VCO) 32, and a divider 34.

The output frequency from the VCO is an integral multiple of the received optical clock frequency, the multiple being dependent on the ratio of the divider 34. A divide-by-M divider 34 will generate an output frequency of M times the received optical clock frequency. Thus the circuit 22 is able to generate a clock frequency considerably higher than the optical clock frequency, and beyond the highest modulation frequency receivable by the photodiode 24.

The size of the illustrated clock re-generation circuit is much greater than that of a storage element. Accordingly, it is preferred that the circuit 22 would be used to feed the locally generated higher frequency clock signal to a plurality of local storage devices. This would allow the skew across the chip to be minimised whilst reducing the area penalty of the clock-regeneration circuit. The exact number of devices clocked by the re-genefation circuit would depend on the trade-off between cell size and the skew that can be tolerated. It will be appreciated that local distribution of the clock by conductive wires or paths will inherently introduce more skew than optical clocking alone.

In this embodiment, the translucent encapsulation 20 serves to diffuse the light from the emitter 18, so that the orientation of the emitter 18 is not critical. The diffusion enables the die to be uniformly illuminated, and can avoid the creation of shadows which might otherwise result from the oblique position of the emitter 18. The encapsulation 20 is covered by an opaque layer 30 to prevent external radiation from interfering with the optical clock signal. The diffusion also enables the light to reach positions on or in the die which are not in line-of-sight with the emitter 18. For example, the light can penetrate to active lower layers of the die 14 on which some of the photodiodes 24 may be formed, and to reach the sides of the die.

In this embodiment, the emitter 18 is positioned adjacent to, and symmetrically relative to, the die 14 to reduce signal skew. However, in other embodiments, the emitter may be arranged at a greater distance from the die, or non-symmetrically relative to the die.

In this embodiment, the emitter 18 is mounted in almost the same plane as the die 14, so that the height profile of the device 10 is not substantially increased.

Moreover, the upper region of the device is left clear for mounting a heatsink, if desired. In an alternative embodiment, the emitter could be mounted below the upper face 14a of the die 14, and the diffusion caused by the translucent encapsulation 20 could spread the light over the die 14.

In another alternative embodiment the emitter 18 may be mounted above the die 14 and point downwardly (as depicted in phantom in Fig. 1 by numeral 32). Such an arrangement can reduce signal skew even further, but might not be practical if a heatsink is desired to be mounted.

The emitter 18 may be implemented as a light emitting diode, or as a laser diode, or as any other suitable device capable of be operated at a desired switching speed. The emitter may emit radiation in the visible wavelength range or, for example, in the infra-red wavelength range.

The photodiode 24 can be integrated very simply, because all metal oxide semiconductor (MOS) active devices have a photoelectric effect. All that is required is a different type of layout structure from conventional transistors to maximise this effect. To ensure that other MOS devices are not affected by the light signals. an additional opaque layer may be added to the top of the die during the manufacturing process. Holes would be created in the opaque layer to allow light penetration to the areas of the photodiodes. This technique is not limited only to MOS devices, as other semiconductor devices exhibit similar photo-sensitivity.

It will be appreciated that the foregoing description is merely illustrative of a currently preferred embodiment, and that many modifications may be made without departing from the principles of the invention. In particular, the package construction, the arrangement of the optical emitter(s) and of the optical receivers, and the die may vary with different device styles and semiconductor implementations. In one alternative form, the package may be omitted, and the integrated circuit mounted directly on a circuit board as a so-called "chip on a board". The die would be glued to the circuit board, and solder corrections made. The LED source would then be mounted adjacent to the die, and the circuit sealed using translucent material topped with an opaque cover.

It will be appreciated that the invention, particularly as described in the preferred embodiments, can enable relatively high frequency clock signals to be used in an optically clocked integrated circuit. The use of optical clocking ensures that there is very little skew between different areas of the chip. Within each area, a second (e.g. higher) clock frequency can be generated which is synchronised to the low skew optical signal.

While features believed to be of importance have been identified in the appended claims, the Applicant claims protection for any novel feature or combination of features described herein and/or illustrated in the accompanying drawings, irrespective of whether emphasis has been placed thereon.

Claims

CLAIMS 1. An integrated circuit device comprising an integrated circuit die, optical means for distributing a clock signal to different areas of the die, and at least one clock regeneration circuit for receiving the optical clock signal and for generating a second clock signal synchronised to the optical clock signal and having a different frequency therefrom.
2. A device according to claim 1, wherein the clock regeneration circuit comprises a phase locked loop circuit.
3. A device according to claim 1 or 2, wherein the clock regeneration circuit is operable to generate a clock frequency being an integer multiple of the optical frequency.
4. A device according to claim 1, 2 or 3, wherein the optical means comprises a first optical receiver implemented in or on a first area of the die for producing a first electronic signal from an optical signal, and second optical receiver means implemented in or on a second area of the die for producing a second electronic signal from the optical signal.
5. A device according to claim 4, wherein each of said optical receivers comprises a photosensitive active semiconductor element.
6. A device according to any preceding claim, further comprising a plurality of data handling elements clocked by the or each clock re-generation circuit.
7. A device according to claim 6, wherein at least one of the data signal handling circuits comprises a data storage register.
8. A device according to any preceding claim, comprising an optical emitter for emitting an optical signal to the die.
9. A device according to claim 8, wherein the optical emitter comprises a light emitting diode.
10. A device according to claim 8, wherein the optical emitter comprises a laser diode.
11. A device according to claim 8, 9 or 10, wherein the optical emitter is carried by a device which supports the die.
12. A device according to claim 8, 9, 10 or 11, wherein the optical emitter is mounted to illuminate the die from one side.
13. A device according to any of claims 8 to 12, wherein the optical emitter is mounted above the face of the integrated circuit die.
14. A device according to any of claims 8 to 13, wherein the optical emitter is coupled to be driven by a signal applied through one or more external terminals of the integrated circuit device.
15. A device according to any preceding claim, wherein the optical means comprises an optically transparent or translucent material for communicating the optical signal to the surface of the die.
16. A device according to claim 15, wherein the die is at least partly encapsulated by the transparent or translucent material.
17. A device according to any preceding claim, wherein the die has an opaque mask with openings defining areas of the die intended to receive the optical signal.
18. A circuit element for an optically clocked integrated circuit, the circuit element comprising an optical receiver for receiving an optical clock signal, and a clockregeneration circuit for generating a second clock signal from the optical clock signal.
19. A circuit element according to claim 18, wherein the clock regeneration circuit comprises a phase locked loop circuit.
20. A circuit element according to claim 18 or 19, wherein the clock regeneration circuit is operable to generate a clock frequency being an integer multiple of the optical frequency.
21. A circuit element according to claim 18, 19 or 20, further comprising a plurality of storage registers clocked by the clock re-generation circuit.
22. An integrated circuit device, or a circuit element therefore, substantially as hereinbefore described with reference to any of the accompanying drawings.