GB2193854A

GB2193854A - Electrostatic discharge protection circuit

Info

Publication number: GB2193854A
Application number: GB08713972A
Authority: GB
Inventors: Leslie Ronald Avery
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1986-06-17
Filing date: 1987-06-16
Publication date: 1988-02-17
Also published as: DE3720046A1; GB8713972D0; KR880000972A; FR2600219A1; IT8720922A0

Description

GB2193854A 1 SPECIFICATION substrate into the active area on the IC. Fur

ther, a large ESID can even destroy IC conduc Electrostatic discharge protection circuit tors.

It is therefore desirable to have a circuit that The present invention is a protection circuit, 70 provides better ESD protection for an IC with and more particularly one that is suitable for less likelihood of substrate current injection integrated circuits (ICs). and distruction of conductors.

Electrostatic discharge (ESD) is a serious In accordance with the present invention an threat to the reliability of ICs, particularly of integrated circuit comprises a pair of supply the metal oxide semiconductor (MOS) family 75 rails, a plurality of signal pins, a first plurality due to the high impedances involved which do of circuits coupled between said supply rails, not permit leakage currents appreciable and a second plurality of circuits disposed ad enough to safely dissipate electrostatic vol- jacent said signal pins, respectively, and coup tages. led between said signal pins, respectively, and One type of ESD IC protection circuit uses a 80 said first plurality of circuits, respectively, for plurality of series connected current limiting protecting said first plurality of circuits, re resistors that are series coupled between the spectively, against damaging transients, each gate electrode of an MOS field effect transis- of said second plurality of circuits comprising tor (MOSFET) and a signal input pin and a a snap-back diode coupled between said rails.

plurality of diodes coupled between said resis- 85 The sole figure of the accompanying draw- tors or pin and the power supply rails for the ing schematically illustrates an embodiment of MOSFET. This protection circuit works well the invention.

when the IC is plugged into a circuit board Shown in the figure is an IC 10 having and either the board has power supply de- therein a pair of supply rails 12 and 14 that coupling capacitors, or the board is connected 90 are connected to power pins 16 and 18, re to a power supply. In particular, at least one spectively, of the IC 10. Typically, the rail 12 of the diodes will conduct in the forward has about 5 volts thereon, while the rail 14 mode and a relatively large value power sup- has about zero volts (ground) thereon. A first ply filter capacitor or the board decoupling plurality of circuits 20 is connected between capacitor provides a low impedance return for 95 the supply rails 12 and 14 and comprises the the transient diode current so that the ESD is circuits 20a and 20b; similarly, a second plu clamped to one of the respective rail voltages rality of circuits 22 is also connected between depending upon its polarity. However, if the IC the supply rails 12 and 14 and comprises the is not plugged or wired into the board, or the circuits 22a and 22b, which protect the circu IC is attached to the board but the board is 100 its 20a and 20b, respectively, against ESD.

not plugged into the power supply and no Although the circuits 22a and 22b are shown decoupling capacitor is present on the board, as being identical, this is not necessary. Fur then inherent parasitic diodes and, for comple- ther, although only two circuits 20a and 20b mentary MOSFETs (CMOS), parasitic silicon are shown for the plurality 20, in practice controlled rectifiers (SCRs) having typical 105 there will be many such circuits.

breakdown voltages of 40 to 80 volts must The circuit 20a comprises a CIVIOS pair of be relied upon to complete the return path for P-channel (PMOS) and N- channel (NMOS) FETs the ESD. This has proved adequate for MOS 24 and 26, respectively. The FET 24 has its devices having a minimum feature size (gate source 28 connected to the rail 12, its gate length) of at least 5 micrometers (u). 110 30 connected to the gate 32 of the FET 26, However, recently there have been efforts and its drain 34 coupled to the drain 36 of to make ICs with ly and even smaller gate the FET 26. The gates 30 and 32 receive an lengths that have typical drain-source breakinput signal from a signal pin 40 via the circuit down voltages of 8 to 7 volts. The parasitic 22a, while the drains 34 and 36 provide an devices have breakdown voltages that are too 115 output signal on a line 42 to other circuits high to protect these IC MOS devices. Further, (not shown) within the ' IC 10. The source 38 modern processing techniques, such as dielec- of the FET 26 is connected to the rail 14.

tric isolation and epitaxial fabrication on a The circuit 20b comprises a pair of NMOS highly doped substrate, often totally eliminate FETs 44 and 46, with the FET 46 connected the parasitic SCRs. 120 to act as a depletion load for the FET 44. In An intentional diode having a low breakparticular, the FET 46 has its drain 48 con- down voltage, e.g. 10 volts at low current, nected to the rail 12, and its gate 50 con but exhibiting a snap-back characteristic at nected to its source 52, and to the drain 54 high current levels, can be formed and con- of the FET 44, and also to a line 60 for nected between the power rails of the IC to 125 providing an output signal to other circuits supply the return path for ESID. However, the (not shown) within the IC 10. The gate 56 of stray resistance and inductance of the power the FET 44 receives an input signal from a rails can reduce the effectiveness of the diode signal pin 62 via the circuit 22b. The source during the ESID, which can result in malfunc- 58 of the FET 44 is connected to the rail 14.

tion of the IC due to current injection from the 130 The circuit 22a is disposed adjacent the pin 2 GB2193854A 2 40, typical within 500 microns, and comprises If V, goes negative with respect to the rail a first impact ionization snap-back diode -64 12, then when this voltage difference reaches having its cathode and anode coupled to the 10 volts, the diode 66 will breakdown and rails 12 and 14, respectively. By "impact ioni- start conducting in the reverse direction.

zation snap-back diode" is meant a diode 70 When 10.7 volts is reached due to the inher which exhibits two stable breakdown voltages, ent resistance of the diode 66, the diode 64 one at low current levels and a lower sustain- will breakdown and reverse conduct and the ing voltage at higher current levels due to im- diodes 68, 74, and 76 will forward conduct.

pact ionization. Such a diode can comprise As the transient current increases, impact ioni- positive-intrinsic-negative (PIN) conductivity 75 zation occurs in the snap-back diodes and the type semiconductor regions. However, such breakdown voltage snaps back to a lower diodes are difficult to fabricate in an integrated value. Thus the diodes and the resistors 70 circuit. Therefore, a lightly doped P or N con- and 72 will absorb the current produced by ductivity type region is frequently substituted V,, thereby protecting the circuit 20a. N for the I conductivity type region; Such diodes 80 If Vi goes positive with respect to the rail exhibit snap-back characteristics similar to PIN 14, then when this voltage difference reaches diodes and are commonly known as "Read" 10 volts, the diodes 68, 74, and 76 will diodes. A second snap-back diode 66 has its breakdown and reverse conduct. When Vi cathode connected to the rail 12 and its an- reaches 10.7 volts due to the inherent resis ode connected to the pin 40. A third snap- 85 tance of the diode 68, then the diode 66 back diode 68 has its cathode connected to forward conducts and the diode 64 will break the pin 40 and its anode connected to the rail down and reverse conduct, thereby protecting 14. A first resistor 70 has one end connected the circuit 20a.

to the pin 40 and its other end connected to If Vi goes negative with respect to the rail one end of a second resistor 72 and the cath- 90 14, then the diode 68 forward conducts at ode of a fourth snap-back diode 74. The 03 volt and clamps Vi to this voltage, thus other end of the resistor 72 is connected to protecting the circuit 20a.

the cathode of a fifth snap-back diode 76 and If the voltage on the rail 12 goes positive to the gates 30 and 32. The anodes of the with respect to the rail 14, then when it diodes 74 and 76 are connected to the rail 95 reaches 10 volts, the diode 64 will reverse 14. conduct, thus clamping the voltage. If the vol- Although not necessary, the circuit 22b is tage on the rail 12 goes negative with respect identical to that of the circuit 22a and is dis- to the rail 14, then when it reaches 0.7 volt, posed adjacent to the pin 62 and therefore the diode 64 forward conducts, thus clamping will not be separately described. Correspond- 100 the voltage. In either case, the circuit 20a is ing elements have been given corresponding protected.

reference numerials with the suffix "a" added. The operation of the circuit 22b in protect- The initial breakdown voltage for all of the ing the circuit 20b is identical to that de- snap-back diodes can be matched to the cir- scribed above and therefore will not be de cuit requirements by selecting the width of the 105 scribed.

I or lightly doped regions and is, e.g., about It will therefore be appreciated that by pro- volts, which is slightly less than the breakviding a diode such as diodes 64 and 64a in down voltage of about 12 to 14 volts of two the circuits 22a and 22b, respectively, and series connected FETs, e.g. 24 and 28 or 44 disposing the circuits 22a and 22b near the A and 46, having ly gate length. In general, the 110 signal pins 40 and 62, respectively, a high _J1 smaller the gate length, the lower the breakdegree of protection is afforded the circuits down voltage of the FETs. In order to provide 20a and 20b, respectively, by providing a 1A protection, the snap-back diodes should have short return path for ESD or other similar both high and low current breakdown voltages damaging transients, e.g., on a power line, of less than the breakdown voltage of the 115 regardless of the stray inductance or resis series connected FETs. tance of the rails 12 and 14. Further by mak- In operation, it is assumed that the IC 10 is ing all of the diodes snap- back diodes, a either not plugged or wired into a circuit lower transient voltage for a high transient board or if so, then there is no decoupling current is imposed on the protected circuits as capacitor on the board, and therefore a tran- 120 compared to normal Zener or avalanche di sient electrostatic voltage can occur producing odes.

a transient current due, e.g., from handling,

Claims

between the pins 40 or 62 and the supply CLAIMS rails 12 or 14. 1. An

integrated circuit comprising:

Consider first that an increasing positive vol- 125 a pair of supply rails; tage occurs at the pin 40 (hereinafter called a plurality of signal pins; "Vi") with respect to the rail 12. When V.1 a first plurality of circuits coupled between reaches 0.7 volt, the diode 66 will conduct in said supply rails; and the forward direction, thereby clamping Vi to a second plurality of circuits disposed adja- 0.7 volt and thus protecting the circuit 20a. 130 cent said signal pins, respectively, and coup- 3 GB2193854A 3 led between said signal pins, respectively, and said first plurality of circuits, respectively, for protecting said first plurality of circuits, re spectively, against damaging transients, each of said second plurality of circuits comprising a first snap-back diode coupled between said rails.
2. The circuit of claim 1 wherein one of said first plurality of circuits comprises a P channel field effect transistor and an N-channel field effect transistor series coupled to said P channel transistor, the gates of said transis tors being coupled together and to one of said second plurality of circuits.
3. The circuit of claim 1 wherein one of said first plurality of circuits comprises a pair of series coupled field effect transistors of the same conductivity type, the gate of one of said transistors being coupled to the source thereof, the gate of the remaining transistor being coupled to one of said second plurality of circuits.
4. The circuit of claim 3 wherein said con- ductivity type is N-type.
5. The circuit of claim 1 wherein one of said second plurality of circuits further com prises second and third snap-back diodes coupled between one of said pins and said supply rails, respectively.
6. The circuit of claim 5 wherein said one circuit further comprises a first resistor coup led to said pin, and a fourth snap-back diode coupled between said resistor and one of said supply rails.
7. The circuit of claim 6 wherein said one circuit further comprises a second resistor coupled to said fourth diode, and a fifth snap back diode coupled between said second re sistor and said one rail.
8. The circuit of claim 7 wherein said first, third, fourth, and fifth diodes each have the same type electrode coupled to said one rail.
9. The circuit of claim 8 wherein said same type electrode comprises an anode.
10. An integrated circuit provided with pro- tection substantially as hereinbefore described with reference to the accompanying drawing.

Published 1988 at The Patent Office, State House, 66/71 HighHolborn, London WC 1 R 4TP. Further copies may be obtained from The Patent Office, Sales Branch, St Mary Cray, Orpington, Kent BF15 3RD.

Printed by Burgess & Son (Abingdon) Ltd. Con. 1/87.