GB2184617A - Fast frequency switching fractional synthesizer - Google Patents
Fast frequency switching fractional synthesizer Download PDFInfo
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- GB2184617A GB2184617A GB08519193A GB8519193A GB2184617A GB 2184617 A GB2184617 A GB 2184617A GB 08519193 A GB08519193 A GB 08519193A GB 8519193 A GB8519193 A GB 8519193A GB 2184617 A GB2184617 A GB 2184617A
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- 230000015572 biosynthetic process Effects 0.000 description 6
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
- H03L7/1978—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider using a cycle or pulse removing circuit
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A frequency synthesiser includes a phase-lock loop with a programmable divider 17 and a pulse deleter 18 clocked at a programmable rate by a rate multiplier 19 receiving divider output pulses. Means 20, 21 (also Fig. 3) are provided for compensating phase jitter caused by each pulse deletion by adding a cancelling signal to the output of comparator 11. The comparator (Fig. 4) has a wide response (greater than +/-2 pi ) and may utilise counters to give a digital output; a control processor (Fig. 5) may switch the comparator gain, or preset a digital input thereto, to speed acquisition. <IMAGE>
Description
SPECIFICATION
Fast frequency switching fractional synthesizer
FIELD OF THE INVENTION
This invention relates to a frequency synthesizer and, more particularly, to a type of "fractional-N" synthesizer.
DESCRIPTION OF THE PRIOR ART
For a high resolution indirect frequency synthesis, a long chain of programmable counters inserted in the feedback path produces a very low frequency feedback signal for phase comparison. This emphasizes the difficulty of loop filter design and the requirement of a stable voltage controlled oscillator. Thus a type of "fractional-N" synthesis is applied for a high resolution requirement. The detail operation is stated in a text book "Frequency
Synthesis by phase lock" by William F. Egan. The frequency resolution is divided by two portions. The higher frequency portion provides a count ratio for the standard resettable counter in the feedback path. The lower frequency portion provides an input of a digital accumulator. The accumulator adds the input with its accumulated output each time by the phase detector's reference frequency.For every carry signal generated by this accumulator, a pulse is deleted from the input signal of said presettable counter. The low frequency jitter due to the pulse delete is reduced by adding a low level signal which corresponds to the value of the accumulator to the voltage controlled oscillator.
First of all, the accumulator requires complex parallel adders and latches especially if the accumulator is a long one and BCD (binary coded decimal data) type. Secondly, the jitter reducing signal related to the accumulator's content which is a ramp signal with random peak values does not fully compensate the effect introduced by the pulse delete jitter. After filtered by the phase locked loop's filter and integrated by the voltage controlled oscillator, the magnitude of the phase jitter does not foilow the value in the accumulator. Besides, a waiting or justification jitter whose spectrum's frequencies start from a very low frequency is created due to an accumulation of the difference of the compensation signal's peak values in the loop's filter.Finally, in order to approach the performance of a direct frequency synthesis, a fast locking or frequency switching is not possible due to the large time constant of the loop's low pass filter.
SUMMARYOFTHE INVENTION
The present invention provides an indirect frequency synthesis similar to the stated "fractional
N" synthesizer with a simpler circuit and higher performance. Although most synthesizers are convenient to enter frequency control in terms of
BCD digits, the accumulation of BCD digits applying
BCD parallel adders is complex and expensive.
Otherwise, a code translation of BCD to binary logic is required. The present invention applies a type of rate multiplier which accepts binary or BCD input directly and produces the output equivalent to the accumulator's carry output without complex arithmetic logic.
A broad phase/frequency comparator is applied in the invention to convert a broad phase/frequency difference (phase difference may exceed i2rE radians) of two inputs into an almost direct current signal without any effective signal filtering. As a result, the phase/frequency loop may be connected with no or a very small time constant loop's low pass filter. Thus a fast locking or frequency switching is possible. Due to the nature of broad range of phase/frequency comparation, the problem of cycie slipping in traditional phase locked loop does not normally happen.As a further advantage, the phase step or pulse delete effect is reduced or scaled by this broad phase/frequency comparator to an insignificant level before the error signal applies to the voltage controlled oscillator and no compensation or correction signal for the pulse delete action is not normally required. On the other hand, this broad phase/frequency comparator may be aided by an external logic means or processor means to achieve a frequency switching fast enough to compare with a direct frequency synthesis.
Finally, as to enhance the further performance, an anti-step network triggered by the pulse delete signal generates a synchronous casual transient to cancel the pulse delete effect in the phase/frequency locked loop and the loop accumulates no low frequency or waiting jitter of the frequency output.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of the present invention will be more readily apparent from the following detailed description taken in conjunction with the accompanying drawings.
Figure 1 depicts a block schematic of the invention,
Figure 2 depicts another block schematic of the invention,
Figure 3 depicts a detail schematic of an anti-step network,
Figure 4 depicts a detail schematic of a broad phase/frequency comparator, and
Figure 5 depicts a schematic of a connection between a logic means and a broad phasel frequency comparator.
DETAILED DESCRIPTION
Figure 1 depicts a block diagram of a preferred embodiment according to the invention. A reference signal fr Hz at line 10 is applied to broad phasel frequency comparator 11. The output of comparator 11 which represents a broad phase difference (may exceed +2n radians) or a phase and frequency difference is connected to an input of voltage controlled oscillator 14 via an optional low pass filter 13. The output of VCO 14 at line 15 is fed to an input of pulse delete 18 which represents the pulse deleted signal of VCO 14's output is fed to an input of programmable counter 17. The counter ratio of counter 17 is preset externally as N. Counter 17 may be a cascade of binary or decade counters.
Sometimes, counter 17 may combine with pulse delete 18 to form a type of dual modulus counter.
The output of counter 17 is fed to a feedback input of broad phase/frequency comparator 11 and a clock input of rate multiplier 19 via line 16. The rate multiplier 19 whose multiplying ratio is preset externally as F may be a fractional binary or BCD number. An example is CD4089 from RCA or
Motorola. Of course, this rate multiplier may be also be one applying a continuous parallel adding method which involves parallel adders, accumulator and latches or a processor's adding routine. The output of rate multiplier 19 is fed to pulse delete 18 for requesting a pulse to be deleted from VCO 14's output.
In operation, a stable reference signal source of fur Hz is applied to an input of phase/frequency comparator 11. Detail operation of comparator 11 will be described later. During steady state, the feedback signal at line 16 should equal to fr Hz too.
Since the fractional multiplying ratio input of multiplier 19 is F, frequency output of rate multiplier is fr.F Hz. Since the count ratio of counter 17 is set to be N, frequency of its input must be fr.N Hz. As a result, the output of VCO 14 at line 15 equals to fr.F
Hz + fr.N Hz is achieved where N is an integer and F is a fractional number and both can be programmed externally.
Figure 2 depicts a block diagram of another preferred ambodiment according to the invention.
Most circuits except the following have been described in figure 1 and not repeated. Anti-step network 21 receives inputs from the outputs of VCO 14, pulse delete 18 and reference signal fz Hz at line 10 to generate a synchronous casual transient signal complementary to the pulse delete effect on the broad phase/frequency comparator 11 This transient signal carries equal peak values. The output of comparator 11 is summed with the output of anti-step network 21 by analog adder 20 to cause a cancellation of the pulse delete effect on the comparator 11's output. The output of adder 20 is fed to the input of voltage controlled oscillator 14 via an optional low pass filter 13.
In operation, the circuit functions similar to figure 1 escept a further treatment of the pulse delete effect. The expected error from the output of comparator 11 caused by the pulse delete action is cancelled by anti-step network 21's output. Since the output of anti-step network 21 is synchronous, casual and complementary to the pulse deleted and has equal peak values, there is no accumulation of any low frequency or waiting jitter in the phase/ frequency locked loop.
Now turning to figure 3, an anti-step network is illustrated. Item 30 is a jitter synchronous which receives a signal at line 22 indicating a pulse been deleted from a pulse delete means, a reference signal of fur Hz at line 10 and a feedback clock signal of fr(N + F) Hz at line 15 and produces a synchronous pulse delete signal representing the expected starting period of jitter due to a pulse delete to the phase/frequency locked loop and its duration of one feedback clock period representing an initial phase difference due to pulse delete. The signal from jitter synchronizer 30 is fed to control switch 41 via inverters 3538 and also AND gated with the output of inverter37 at AND gate 39. The output of AND gate 39 is fed to control switch 42.A current source 40 with one end connected to a negative potential source VSS is fed to an input of switch 41. The output of switch 41 is connected to line 23 parallel to switch 42 and linear network 43.
Linear network 43's system order equals to the order of the phase/frequency located loop and normally may be either first or second order depending an insetion of loop's low pass filter.
Linear network 43 shown in figure 3 is a second order one consisting of capacitor 44, inductor 45 and resistor 46. The natural response frequency and damping factor of linear network 43 should equal to corresponding ones of the phase/frequency locked loop. For a first order loop, inductor 45 is not required. Sometimes, for a convenience, the second order response can be approximated to a first order one and inductor 45 may also be eliminated.
When the signal from jitter synchronizer 30 turns high, a narrow pulse at the output of AND gate 39 caused by delay time of inverters 3537 activates switch 42 to discharge the potential at line 23 to provide a casual condition. Thus switch 42 should be a very high speed and low impedance one such as VMOS FET 2N6659 with proper biasing. Then the high signal output of jitter synchronizer 30 delayed by inverters 3538 activates switch 41 to allow a negative current source charging linear network 43.
The negative voltage built up at line 23 before switch 41 released depends on the current source 40's current rate, duration of switch 41 activation and the value of capacitor 44. Thus this negative voltage can be calculated to match the peak value of error caused by the pulse delete at line 12 of figure 2 before summing at analog adder 20. When switch 41 is released, the latched potential reacts to the linear network 43 to produce a casual transient response at line 23. Since the initial potential of this transient depends on the duration of pulse applied at line 15, the peak value of this anti-step signal at line 23 varies with the frequency output of VCO 14 and it corresponding to peak pulse delete error signal generated from comparator 11. Switch 42 functions to discharge the residue each time preventing accumulation of a residual voltage at line 23 by current source 40.The replacement of the current source in the anti-step network by a constant voltage source is possible if frequency output of the voltage controlled oscillator is fixed or with a narrow variable bandwidth. The output of anti-step network may also be emulated by a digital waveform generator which normally consists of a counter, a programmable read only memory and a digital to analog converter.
Now turning to figure 4, a preferred embodiment of a broad phase/frequency comparator is illustrated. Item 50 is a differential latch which receives an input reference signal at line 10 and a feedback signal at line 16. The data D terminals of flip flops 51 and 57 are connected to a high source
PU. The 0 output of flip flop 51 and the output of
NAND gate 54 are connected to inputs of NAND gate 53. The output of NAND gate 53 and OR gate 73 are connected to inputs of NAND gate 54. The 0 output of flip flop 57 and output of NAND gate 59 via inverter 72 are connected to inputs of OR gate 73.
The output of NAND gate 53 and output of NAND gate 56 are connected to AND gate 55. The output of
AND gate 55 is connected to R reset terminal of flip flop 51. The output of NAND gate 53, 0 output of flip flop 51,0 output of flip flop 57 and NAND gate 59 are connected to corresponding inputs of NAND gate 56. The 0 output of flip flop 57 and the output of NAND gate 60 are connected to inputs of NAND gate 59. The outputs of NAND gate 59 and OR gate 57 are connected to NAND gate 60. The 0 output of flip flop 51 and output of NAND gate 53 via inverter 70 are connected to inputs of OR gate 71. Outputs of
NAND gates 59 and 56 are connected to inputs of
AND gate 61. The output of AND gate 61 is connected to R terminal of flip flop 57.
In operation, assuming that a positive edge appears on the signal lead 10, causing the output of flip-flop 51 to go high, if there is simultaneously a low level on the 0 output of flip flop 57, there will be a low level output generated at the output of NAND gate 53. Due to this low level, flip flop 51 is reset and the output of NAND gate 53 turns high again. Thus a narrow low level pulse is generated at the output of
NAND gate 53 or line 62. Similarly, the presence of a feedback positive edge appears on signal lead 16, causing the Q output of flip flop 57 to go high. if there is simultaneously low level on the 0 output of flip flop 51. a similar narrow low level pulse is generated at the output of NAND gate 59 or line 63.
If a positive edge is applied to flip flop 57 on line 16 slightly later than one applied to flip flop 51 at line 10, flip flop 57 will latch the high signal until the generation of a low level pulse at the NAND gate 53 is completed and then the generation of the low level pulse at the NAND gate 59 will be permitted.
Similarly, a positive edge is applied to flip flop 51 slightly later than the one applied to flip flop 57, a low level pulse will be generated at the output of
NAND gate 59 first and then another low level pulse will be generated at the output of NAND gate 53.
If positive going pulse edges arrive at flip flops 51 and 57 at almost same time, the output of NAND gate 56 is connected to reset both flip flops if a latch up race problem or dead lock condition occurs.
Thus the differential latch 30 produces nonoverlapping output pulses at its two outputs in response to pulses applied to its corresponding inputs. It will cancel both inputs at the same time if an unresolved race problem happens.
The reference signal via the differential latch 30 is presented at line 62 and is applied to count-up input
CU of up-down counter 65 via selector 64. The C output of counter 65 is applied via selector 66 to the count-up input CU of up-down counter 67. The feedback signal via the differential latch 30 is presented at line 63 and is applied to count-down input CD of up-down counter 65 via selector 64. The
B output of counter 65 is applied via selector 66 to the count-down CD input of counter 67.
The parallel outputs C of counters 65 and 67 which may be sensed externally are connected to corresponding inputs of digital to analog converter 68. The voltage output of D/A converter 68 is presented at line 12 or the analog output of the broad phase/frequency comparator 11. In a stable condition, the pulse rate at line 62 is the same as the pulse rate at line 63. The parallel outputs of up-down counters 65 and 67 should be a value around two adjacent numbers and causes the output of the D/A converter 68 to have a low amplitude pulse duration modulated signal superimposed on a D.C. signal. If there is any change of phase difference between the reference and feedback signals, the duration of modulated signal will change correspondingly.If there is a broad phase difference (such as one greater than 2rt radians) or an average frequency difference between the reference and feedback signals, the average value of up-down counters 65 and 67 will be caused to count-up or down corresponding to the phase difference or frequency difference. As a result, the output of D/A converter 68 follows the phase or frequency difference between the reference signal at line 10 and the feedback signal at line 16. Also, the phase difference which may be more than 2rt radians has been scaled by the count ratio of the up-down counters 65 and 67.
The selection of sections in the up-down counter can be programmable, by signal line D, thus providing a controllable broad phase/frequency comparator's conversion gain or the phase difference scaling factor.
Selector 64 block output signals from differential latch 30 to counter 67 when the signal is reset at line
D. At this time, output signals from differential latch 30 are routed through selectors 66 to counter 67.
Thus only the most significant bits of counters 65 and 67 are activated. When signal at line D is set, output signals from differential latch 30 are routed to counter 65 through 64. Carry and borrow signals from counter 65 are through selector 66 to counter 67.
The parallel outputs of counters 65 and 67 at line C which are also the digital output of the broad phase/ frequency comparator 11 may also be read, or inputted by external logic or processor means (such as a microprocessor). Any predetermined or inputted value in the external logic or processor means may be loaded into the broad phase/ frequency comparator 11 via parallel input B. This input line B is/are connected to inputs of up-down counters 65 and 67 when a negative logic signal at line A is valid and connected to PL terminals of counters 65 and 67.
Also, counters 65 and 67 can be set to maximum count in the event of a carry C from counter 67, this carry being applied to set S terminal of counters 65 and 67. Counters 65 and 67 can be reset to minimum count in the event of a borrow B from count 67, this borrow signal being applied to reset R terminal of counters 65 and 67. This provides a non-linear limitation ofthe broad phase/frequency comparator's comparing range. The gains of both comparing range's ends are fixed. This is especially useful to cause a fast acquisition related to a type of band-band control action during an external logic aided bandwidth variation acquisition.
Now turning to figure 5, a connection between a logic means or processor means and the broad phase/frequency comparator is shown. The digital output of broad phase/frequency comparator 11 at line C may be read or stored by processor or logic means 80. Similarly, any value or stored value may be preset by logic or processor means 80 to digital input of comparator 11 at line B when signal at line
A is valid. Signal generated at line D by logic means or processor means 80 may select the variable conversion gain of the broad phase/frequency comparator. Logic or processor means 80 may also generates N (count ratio of programmable counter in figure 1 or 2) and F (fractional number of rate multiplier in figure 1 or 2) for the phase/frequency locked loop.
Although a specific embodiment of this invention has been shown and described, it will be understood that various modifications may be made without departing from the spirit of this invention.
An example of modifications is the cancellation of pulse delete jitter effect to a phase locked loop by said anti-step network's output the pulse delete is being done on the input reference signal.
Claims (20)
1. A fast frequency switching fractional synthesizer applying a phase/frequency locked loop comprising:
a) a broad phase/frequency comparator having a first input to receive a reference signal and a second input to receive a feedback signal for producing a signal representing the phase and frequency difference between said inputs,
b) a voltage controlled oscillator receiving the output of said broad phase/frequency comparator's output for producing an output signal having a frequency corresponding thereto,
c) a pulse delete means receiving the output from said voltage controlled oscillator, deleting a clock pulse from it whenever a clock pulse is received from the output of a rate multiplier, and for providing an output of a pulse deleted clock signal,
d) a presettable counter receiving said pulse deleted clock signal, permitting a variable count ratio set externally and providing a divided output signal as the feedback signal which is fed to said second input of said broad phase/frequency comparator and a clock input of the rate multiplier, and
e) said rate multiplier receiving said feedback signal, accepting an externally preset variable multiplying ratio and for providing a fractional multiplied clock pulse output feeding to said pulse delete means.
2. A frequency synthesizer as defined in claim 1 in which the output of the broad phase/frequency comparator is connected to the voltage controlled oscillator via a low pass filter.
3. A frequency synthesizer as defined in claim 1 or 2 wherein said broad phase/frequency comparator includes:
a) a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a count-up input of a digital updown counter, and a second output connected to a count-down input of said counter, said up-down counter having parallel outputs connected to a digital to analog converter having an output for providing an analog output signal representative of a count in said counter,
b) said differential latch being constructed that non-overlapping output pulses are produced at said first and second outputs in response to pulses applied to said first and second inputs, and
c) said differential latch also being constructed that both inputs are cancelled if an unresolved race problem or a dead lock situation happens.
4. The circuit as defined in claim 3 in which said digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output.
5. The circuit as defined in claim 3 further includes:
a) means for transferring the up-down counter's output value to an external logic means or a processor means, and
b) means for presetting the up-down counter's output value from said external logic means or processor means to a particular value.
6. The circuit as defined in claim 3 further includes means for selectively activating a number of updown counter sections from an external logic means or processor means in order to vary said broad phase/frequency comparator's conversion gain.
7. fast frequency switching fractional synthesizer applying a phase/frequency locked loop comprising:
a) a broad phase/frequency comparator having a first input to receive a reference signal and a second input to receive a feedback signal for producing a signal representing the phase and frequency difference between said inputs,
b) an analog adder means connected for summing the output of said broad phase/frequency comparator and an anti-step network's output and causing a cancellation of jitter effect due to pulse delete,
c) a voltage controlled oscillator receiving the output of said broad phase/frequency comparator's output for producing an output signal having a frequency corresponding thereto,
d) a pulse delete means receiving the output from said voltage controlled oscillator, deleting a clock pulse from it whenever a clock pulse is received from the output of a rate multiplier, and for providing an output of a pulse deleted clock signal,
e) a presettable counter receiving said pulse deleted clock signal, permitting a variable count ratio set externally and providing a divided output signal as the feedback signal which is fed to said second input of said broad phase/frequency comparator and a clock input of the rate multiplier,
f) said rate multiplier receiving preset variable multiplying ratio and for providing a fractional multiplied clock pulse output feeding to said pulse delete means, and
g) said anti-step network accepting the output of said pulse delete means for providing a casual transient signal output complementary to the one generated due to pulse delete action by said phase/ frequency comparator.
8. Afrequency synthesizer as defined in claim 7 in which the output of the broad phase/frequency comparator is connected to the voltage controlled oscillator via a low pass filter.
9. A frequency synthesizer as defined in claim 7 or 8 wherein said broad phase/frequency comparator includes:
a) a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a count-up input of a digital updown counter, and a second output connected to a count-down input of said counter, said up-down counter having parallel outputs connected to a digital to analog converter having an output for providing an analog output signal representative of a count in said counter,
b) said differential latch being constructed that non-overlapping output pulses are produced at said first and second outputs in response to pulses applied to said first and second inputs, and
c) said differential latch also being constructed that both inputs are candled if an unresolved race problem our a dead lock situation happens.
10. The circuit as defined in claim 9 in which said digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to a low count upon the presence of a signal at the BORROW output.
11. The circuit as defined in claim 9 further includes means for selectively activating a number of up-down counter sections from an external logic means or processor means in order to vary said broad phase/frequency comparator's conversion gain.
12. The circuit as defined in claim 9 further
includes:
a) means for transferring the up-down counter's output value to an external logic means or a
processor means, and
b) means for presetting the up-down counter's
output value from said external logic means or
processor means to a particular value.
13. A frequency synthesizer as defined in claim 7
or 8 wherein said anti-step network includes:
a) a jitter synchronizer receiving the signal
indicating a pulse been deleted from said pulse
delete means, the reference signal and the feedback
signal, for producing a synchronized pulse delete
signal representing the expected starting period of
jitter due to a pulse delete to the phase/frequency
locked loop and its duration representing an initial
phase difference due to pulse delete,
b) a pulse generator means receiving the edge
signal of said jitter synchronizer's output for
providing a short duration pulse enabling a first
switch means to discharge the residual potential
accumulating in a linear network,
c) a delay means delaying the jitter synchronizer's output to follow said short duration pulse,
d) a second switch means being activated by said delayed signal, for enabling a current source to charge up a potential proportional to the duration of said jitter synchronizer's output across the linear network after the said discharge of residual potential being completed, and
e) said linear network reacting to the charged potential for producing a transient output complementary to the pulse delete system response.
14. A method to achieve a fast locking or frequency switching in a phase/frequency locked loop comprising:
a) comparing a phase and frequency difference of a reference input and a feedback signal by a broad phase/frequency comparator,
b) responding to the output of said broad phase/ frequency comparator by a voltage controlled oscillator via no loop's low pass filter to generate a frequency corresponding thereto, and,
c) feeding the output of the voltage controlled oscillator via if any dividing counterto an input of said phase/frequency comparator as the feedback signal.
15. The method as defined in claim 12 wherein the broad phase/frequency comparator converts and scales the phase and frequency difference of inputs into an output signal comprising a low amplitude pulse duration modulated signal superimposed on a
D.C. signal.
16. A method to achieve a fast locking or frequency switching in a phase/frequency locked loop comprising:
a) comparing a phase and frequency difference of a reference input and a feedback signal by a broad phase/frequency comparator,
b) responding to the output of said broad phase/ frequency comparator by a voltage controlled oscillator via no loop's low pass filter to generate a frequency corresponding thereto,
c) feeding the output of the voltage controlled oscillator via if any dividing counter to an input of said phase/frequency comparator as a feedback signal, and
d) varying the conversion gain successively of said broad phase/frequency comparator from a high value to a low value as to vary the loop's bandwidth from a high frequency one to a low frequency one
by an external logic means or processor means aiding after a frequency switching requirement
being informed.
17. A method to achieve a fast locking or frequency switching in a phase/frequency locked
loop comprising:
a) comparing a phase and frequency difference of
a reference input and a feedback signal by a broad
phase/frequency comparator,
b) responding to the output of said broad phase/ frequency comparator by a voltage controlled
oscillator via no loop's low pass filter to generate a frequency corresponding thereto,
c) feeding the output of the voltage controlled
oscillator via if any dividing counter to an input of
said broad phase/frequency comparator as the feedback signal,
d) learning and storing digital outputs of said broad phase/frequency comparator by an external logic means or a processor means for different particular voltage controlled oscillator's outputs,
e) presetting the digital input of said broad phase/ frequency comparator to a particular value stored before corresponding to a particular frequency output being expected from the voltage controlled oscillator due to a change of the feedback dividing counter's count ratio or the frequency of the reference input, and,
f) responding instantly to the preset output value of the broad phase/frequency comparator by said voltage controlled oscillator to produce the expected output frequency.
18. A method of cancelling a phase step response or jitter effect due to a pulse delete from an input signal of a phase/frequency locked loop and introducing no waiting jitter to its output comprising:
a) accepting an input signal to the phase/ frequency locked loop which carries known deleted pulses,
b) generating a pilot signal indicating a pulse having been deleted from said input signal,
c) triggering an anti-step network from said pilot signal in which a synchronized casual transient output complementary to the phase step response of the phase/frequency locked loop due to a pulse delete is produced,
d) summing the loop's error compensation signal which includes the pulse delete error and said antistep network's output synchronously and causing a cancel of pulse delete error to the control input of a voltage controlled oscillator,
e) connecting other parts of said phase/frequency locked loop in a conventional way, and
f) producing no waiting jitter to the phase/ frequency locked loop's output even if repeated pulse delete actions taking place in a random manner due to the complete cancellation of the pulse delete error and accumulating no difference of random peaks of pulse delete errors in the phasel frequency locked loop's low pass filter.
19. The method as defined in claim 16 wherein the range of broad phase/frequency comparing is limited and provides fixed gains of both comparing ends which aids for a fast acquisition in the phase/ frequency locked loop.
20. The method as defined in claim 14, 16 or 17 further including connecting a low pass filter between said broad phase/frequency comparator and the input of said voltage controlled oscillator to filter any ripple or low amplitude pulse duration modulated signal and/or to reduce the loop's total passband bandwidth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08519193A GB2184617A (en) | 1985-07-30 | 1985-07-30 | Fast frequency switching fractional synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08519193A GB2184617A (en) | 1985-07-30 | 1985-07-30 | Fast frequency switching fractional synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8519193D0 GB8519193D0 (en) | 1985-09-04 |
| GB2184617A true GB2184617A (en) | 1987-06-24 |
Family
ID=10583064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08519193A Withdrawn GB2184617A (en) | 1985-07-30 | 1985-07-30 | Fast frequency switching fractional synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2184617A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0438620A1 (en) * | 1990-01-24 | 1991-07-31 | Siemens Aktiengesellschaft | Method and circuit arrangement for the minimization of an a.c. component in the phase detector output signal of a phase locked loop |
| EP0557799A1 (en) * | 1992-02-27 | 1993-09-01 | Hughes Aircraft Company | Digital error corrected fractional-N synthesizer and method |
| EP0566358A1 (en) * | 1992-04-17 | 1993-10-20 | Hughes Aircraft Company | Low noise frequency synthesizer using half integer dividers and analog gain compensation |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3872397A (en) * | 1973-11-07 | 1975-03-18 | King Radio Corp | Method and apparatus for decreasing channel spacing in digital frequency synthesizers |
| GB1447418A (en) * | 1974-03-29 | 1976-08-25 | Mullard Ltd | Frequency synthesiser |
| GB2068185A (en) * | 1980-01-21 | 1981-08-05 | Philips Electronic Associated | Frequency synthesiser of the phase lock loop type |
| GB2117198A (en) * | 1982-03-19 | 1983-10-05 | Philips Electronic Associated | Frequency synthesiser |
| GB2131240A (en) * | 1982-11-05 | 1984-06-13 | Philips Electronic Associated | Frequency synthesiser |
| US4514705A (en) * | 1980-12-10 | 1985-04-30 | Wandel & Goltermann Gmbh & Co. Kg | Low-noise digitally tunable phase-locked loop frequency generator |
-
1985
- 1985-07-30 GB GB08519193A patent/GB2184617A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3872397A (en) * | 1973-11-07 | 1975-03-18 | King Radio Corp | Method and apparatus for decreasing channel spacing in digital frequency synthesizers |
| GB1447418A (en) * | 1974-03-29 | 1976-08-25 | Mullard Ltd | Frequency synthesiser |
| GB2068185A (en) * | 1980-01-21 | 1981-08-05 | Philips Electronic Associated | Frequency synthesiser of the phase lock loop type |
| US4514705A (en) * | 1980-12-10 | 1985-04-30 | Wandel & Goltermann Gmbh & Co. Kg | Low-noise digitally tunable phase-locked loop frequency generator |
| GB2117198A (en) * | 1982-03-19 | 1983-10-05 | Philips Electronic Associated | Frequency synthesiser |
| GB2131240A (en) * | 1982-11-05 | 1984-06-13 | Philips Electronic Associated | Frequency synthesiser |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0438620A1 (en) * | 1990-01-24 | 1991-07-31 | Siemens Aktiengesellschaft | Method and circuit arrangement for the minimization of an a.c. component in the phase detector output signal of a phase locked loop |
| EP0557799A1 (en) * | 1992-02-27 | 1993-09-01 | Hughes Aircraft Company | Digital error corrected fractional-N synthesizer and method |
| EP0566358A1 (en) * | 1992-04-17 | 1993-10-20 | Hughes Aircraft Company | Low noise frequency synthesizer using half integer dividers and analog gain compensation |
| US5307071A (en) * | 1992-04-17 | 1994-04-26 | Hughes Aircraft Company | Low noise frequency synthesizer using half integer dividers and analog gain compensation |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8519193D0 (en) | 1985-09-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |